LOOP Search Results

Contextual Info: TLE2024, TLE2024A, TLE2024B, TLE2024Y EXCALIBUR HIGH-SPEED LOW-POWER PRECISION QUAD OPERATIONAL AMPLIFIERS D 3 2 6 5 , M A Y 1 9 8 9 - R E V IS E D O C T O B E R 1991 available features Supply Current . . . 1 mA Max High Open-Loop Gain . . . 7 V/jiV 137 dB Typ

T5CD

Contextual Info: U M C U M 2661 Enhanced Programmable Communications Interface EPCI Features • Automatic serial echo mode (échoplex) ■ Local or remote maintenance loop back mode Baudrate: de to IM bps (1X clock) - de to 62.5K bps (16X clock) - de to 15.625K bps (64X clock)

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS378-APRIL 1994 ' Low Output Skew for Clock-Distribution and Clock-Generation Applications DL PACKAGE TOP VIEW * Operates at 3.3-V Vcc u ’ Distributes One Clock Input to Six Outputs ' One Select Input Configures Up to Three

Contextual Info: TLP115 GaAÄAs IRED a PHOTO-IC T E N T A T I V E DA T A HIGH SPEED, LONG DISTANCE ISOLATED LINE RECIVER MICROPROCESSOR SYSTEM INTERFACES DIGITAL ISOLATION FOR A/D, D/A CONVERSION COMPUTER-PERIPHERAL INTERFACES GROUND LOOP ELIMINATION The T O S H I B A M I N I FLAT C O U PLER TLP115 is a strall outl i n e

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _SCAS337B- FEBRUARY 1 9 9 3 - REVISED NOVEMBER 1996 * f • • • • • • Low Output Skew for Clock-Dlstrlbutlon and Clock-Generation Applications Operates at 3.3-V Vqc Distributes One Clock Input to IWelve

Contextual Info: GaA«As IRED a PHOTO-IC 6N138,139 6N138 CURRENT LOOP DRIVER. U n it in mm LO W INPUT CURRENT LINE RECEIVER. C M O S LOGIC INTERFACE. The T O S H IB A 6N138 and 6N139 consists of a G a A fA s infrared em itting diode coupled w ith a split-Darlington output configuration.

3Y20

Contextual Info: SN75186 QUADRUPLE DRIVER/RECEIVER WITH LOOPBACK D3389. FEBRUARY 1990 FN PACKAGE Meets Standards RS-232-C, EIA-232-D, and CCITT V.28 TOP VIEW Four Independent Drivers and Receivers CM O Ü z S I—JI—] L J L J , A 3 2 1 1 LB ] 5 N < Loopback Mode Functionally Self-Tests

CDC2510A

Contextual Info: CDC2510A 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS604A– APRIL 1998 – REVISED JUNE 1998 D D D D D D D D D D PW PACKAGE TOP VIEW Spread Spectrum Clock Compatible 100 MHz Maximum Frequency Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for

Contextual Info: CDC586 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

Contextual Info: CDC2586 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998 D D D D D D Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V VCC Distributes One Clock Input to Twelve

scas640

Contextual Info: CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640 – JULY 2000 D D D D D D D D D D D D Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications Spread Spectrum Clock Compatible Operating Frequency: 24 MHz to 200 MHz Low Jitter Cycle-cycle : <|150 ps| Over the

zero flux current sensor

Contextual Info: CSNA111 CSN Series closed loop current sensor, measures Actual product appearance may AC, DC or impulse current, vary. 50 A nominal, ± 70 amp range, 1000 turn Potential Applications Features • • • • • • • • Current sensing up to 1200 amps

Contextual Info: OPA 177 OPA177 OPA 177 Precision OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● LOW OFFSET VOLTAGE: 25µV max ● LOW DRIFT: 0.3µV/°C ● PRECISION INSTRUMENTATION ● DATA ACQUISITION ● HIGH OPEN-LOOP GAIN: 130dB min ● LOW QUIESCENT CURRENT: 1.5mA typ

Contextual Info: THS4303 www.ti.com SLOS421B – NOVEMBER 2003 – REVISED JANUARY 2005 WIDEBAND FIXED-GAIN AMPLIFIER FEATURES APPLICATIONS • • • • • • • • • • • • • • Fixed Closed-Loop Gain Amplifier – 10 V/V 20 dB Wide Bandwidth: 1.8 GHz High Slew Rate: 5500 V/µs

PC133 registered reference design

Contextual Info: CDCF2509 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE TOP VIEW this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

MH88617AV-PI

Contextual Info: MH88617 <§> MITEL Programmable SLIC with Advance Information Ringing Amplification ISSUE 2 Features • • Fully programmable line impedance,network balance impedance and gains. Programmable loop current with long loop capability 2-4 Wire conversion. Power down and wake up.

Contextual Info: Quality Semiconductor, I nc. QS5940 SuperSync PCI Controller PLL Clock Driver PRELIMINARY FEATURES/BENEFITS DESCRIPTION • • • • • • • • • • • QS5940 is a high-performance, low skew, low jitter phase-locked loop PLL clock driver. Two banks of

IR3541

Abstract: intel VR12 tray qfn 6x6 CHL8510 programmable digital pwm I2C multiphase pwm323
Contextual Info: Digital Multi-Phase Buck Controller FEATURES DESCRIPTION • 5-phase dual output PWM Controller  Phases are flexibly assigned between Loops 1 & 2  Intel VR12, AMD® 400kHz & 3.4MHz SVI and Memory modes  Dual OCP support for I-spike enhanced AMD CPUs

Contextual Info: Model 10012-6 In-Line Style Applications_ • Subassemblies  Lab Systems  Leveling Loops  Power Monitoring  Test and Calibration Features_        Military Grade 0.125 – 0.25 GHz In-Line Configuration

220v circuit diagram electronic ballast

Abstract: Linear dimming ballast PT5623 FLUORESCENT LAMPS CFLS Ignition Driver IC ptc fluorescent ballast PREHEAT electronic ballast ic
Contextual Info: PT5623 Linear Dimming on/off Ballast Controller DESCRIPTION The PT5623 is an electronic ballast controller IC intended for linear dimming product with ordinary switch. The features of the controller IC include closed-loop dimming control of the lamp current,

Phase Discriminators

Abstract: Phase locked loops MIL-E-5400
Contextual Info: Model 20756 Without Video Amplifier Applications_ • Instantaneous Phase and Amplitude  Phase Locked Loops  S Parameter Measurements  Digital Phase Monitors Features_         2.0 – 4.0 GHz Excellent Phase Accuracy

Contextual Info: CDC536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS _ SCAS378D - APRIL 1994 - REVISED APRIL 1996 • Low-Output Skew for Clock-Dlstrlbution and Clock-Generation Applications • • • Operates at 3.3-V Vqc Distributes One Clock Input to Six Outputs

L01ZXXXS05

Abstract: L01Z***S05 L01Z200S05
Contextual Info: Issued by Module Components Div, TAMURA CORPORATION Hall Effect Current Sensors L01Z*S05 Series Features: •     Advantage: Open Loop type Printed circuit board mounting Unipolar power supply Aperture for cable or bus bar Insulated plastic case according to

L18P***D15

Abstract: L18PXXXD15 L18P050 L18P L18P030 L18P025 L18P003 L18P 060 D15 l18p050d15 L18P020
Contextual Info: Issued by Module Components Div, TAMURA CORPORATION Hall Effect Current Sensors L18P*D15 Series Features: Advantage: •              Open Loop type Printed circuit board mounting Integrated primary Voltage output Busbar version from 40A to 60A