LH53C Search Results

sharp mask rom

Contextual Info: LH53C16600 16M Mask ROM Ref No.: NP 188C Issue Date: September 1997 High-Speed 16M-bit Mask-Programmable ROM with Page Mode Operation LH53C16600 • ■ Description The LH53C16600D/N User’s No. : LH-5C76XX is a CMOS 16M-bit mask-programmable ROM organized as 2 097 152 X 8

marking code GIF

Abstract: NMB MANUFACTURER DDEE177 LH53C8600N CD0-D15
Contextual Info: SHARP LH53C8S00N C L O N T E N T S General Description P. 2 2. Features P. 2 3. Block Diagrai P. 3 4. Pin Connections P. 4 5. Pin Description P. 4 6. Absolute laxiauatatings P. 5 7. Operating Kanges P. 5 î, P.C. Electrical Characteristics P.5 9. A. C. Electrical Characteristics

Contextual Info: LH53CV32800T 32M Mask ROM Model No.: LHME53xx Spec No.: EL097130 Issue Date: July 28, 1998 SHARP LH53CV32800T •Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited

Contextual Info: LH53C32600N 32M Mask ROM Model No.: LHMC56xx Spec No.: EL097186 Issue Date: August 5, 1997 SHARP LH53C32600N # Handle this docuaent carefully for it contains aaterial protected by international copyright law. Any reproduction, full or in part, of this laterial is prohibited

Contextual Info: LH53CV32P00 FEATURES • 4,194,304 x 8 bit organization Byte mode: BYTE = VIL 2,097,152 × 16 bit organization (Word mode: BYTE = VIH) • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) • Supply current: – Operating: 100 mA (MAX.)

Contextual Info: LH53CV16P00 FEATURES • 2,097,152 x 8 bit organization Byte mode: BYTE = VIL 1,048,576 × 16 bit organization (Word mode: BYTE = VIH) • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) • Supply current: – Operating: 85 mA (MAX.)

flash 64m

Contextual Info: MEMORIES Mask ROMs C a p a c ity Access time C o nfig u ra tio n 120ns 100ns 80ns 150ns 256kj I 32k x 8 ] LH53259 12k I 64k x 8 LH53517 128k x 8 LH530800A LH531V00 1M LH531024 64k x 16 i LH532100B-1 256k x 8 ! LH532100B 2M JEDEC standard EPROM pinout 128k x 161

AA1050

Abstract: marking code maxim label
Contextual Info: SHARP SPEC No. E L 0 9 9 1 9 3 ISSUE: Nov. 26 1997 To ; S P E C I F I CAT I O N S Product Type 8M b it MASK ROM LHMC8 6 xx Model No. L H 5 3 C 8 6 00N &This specifications contains 14 pages including the cover and appendix If you have any objections, please contact us before issuing purchasing order.

LQ070T5BG01

Abstract: LM24P20 LM162KS1 BSCR86L00 IR2C07 LM5Q31 IR3Y29B BSCU86L60 lq6bw lq6bw506
Contextual Info: INDEX 1 0 4 - 1 0 9 _ DC_ GL1PR112.69 GL3KG63. 66 GL5EG41.66 1 0 4 - n 0 5 O o c .113 DC1B1CP. 100 GL1PR135.69 GL3KG8. 66

Contextual Info: MEMORIES ★ Capacity Configuration * 1 C om patible with 4 M -bit flash m em ories from A d vanced M icro D evices, Inc. * 2 C om patible with 4 M -bit flash m em ories from Intel Corp. A c c e s s tim e Under development MEMORIES ★ Under development Access time

IR3Y29B

Abstract: ir3y26a1 IR4N IR3T24N IR3C08N ir2c53 ir2c05 li3301 IR3Y08 IR2E02
Contextual Info: Index Model No. IR3T ARM710 ARM7DI ARM7DM ARM7TDMI ARM7TDMI-SPL ARM8 ARM810 CMOS CMOS CMOS CMOS F series G series J series K series ID22 series ID222XX ID223XX ID224XX ID226XX ID227XX ID229XX ID22DXX ID22FXX ID22HXX ID240 series ID240DXX ID240EXX ID240GXX

Contextual Info: CMOS 32M 4M x 8/2M x 16 MROM FEATURES • 4,194,304 x 8 bit organization (Byte mode: BŸTË = V,L) 2,097,152 x 16 bit organization (Word mode: BYTE = V,H) • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) • Supply current: -O p e ra tin g : 100 mA (MAX.)

lh5359

Abstract: e5bx
Contextual Info: Ffe MASK ROM * ★ • MASK ROMs New product Under development * Features • Product lineup covers 11 capacity ranges from 256 k-bit to 128 M-bit. • Product variations with 3 types o f pinout including JEDEC standard EPROM, Mask ROM specific and Flash memory compatible pinout.

sharp mask rom

Abstract: mask rom compatible pinout
Contextual Info: MEMORIES M ask ROMs ★ Mask ROM Specific Pinout • 3 V 3 .3 V operation Capacity Bit configuration A ccess time • 5 V operation Capacity Bit configuration Access time Under development MEMORES ★ Underdevelopment I Page Mode Specification (Mask ROM Specific Pinout)

IR2E27A

Abstract: IR2C53 IR2E02 IR2E27 IR2E10 IR3N34 IR2E31A IR2E01 IR2C07 ir2e31
Contextual Info: lndeX Model No. ARM7D CPU Core28,32,33 ARM7DM 28,33 CMOS CMOS CMOS CMOS 76 5A A F G 44 44 44 44 ID1 series ID2 series ID3 seríes ID21K064 ID21K128 ID21K256 ID21K512 ID21M010 ID21M015 ID21M020 ID21M040 ID22K256 ID22K512 ID22M010 ID22M020 ID22M040 ID22M080

Contextual Info: CMOS 16M 2 M x 8/ 1M x 16 MROM FEATURES PIN CONNECTIONS • 2,097,152 x 8 bit organization (Byte mode: BYTE = V,L) 1,048,576 x 16 bit organization (Word mode: BYTE = V,H) 48-PIN TSOP (Type I) BYTE C A-I6 C A15 IZ • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.)

LHMD09

Contextual Info: MEMORIES ★ U nderdevelopm ent • Page Mode Specification Mask ROM Specific Pinout • 3 .3 V operation B it C apacity configuration 8M 16M x 8/x 16 x 8/x 16 x 16/x 32 x 8/x 16 32M x 16/x 32 64M x 16/x 32 128M x 16/x 32 Model No. LH53BV8600D/N LH53BV8600T

sharp mask rom

Abstract: mask rom 44-pin
Contextual Info: LH530800A I CMOS 1M 128K x 8 Mask Programmable ROM FEATURES • 131,072 x 8 bit organization • Access time: 150 ns (MAX.) • Power consumption: Operating: 193 mW (MAX.) Standby: 550 (iW (MAX.) • Fully static operation • TTL compatible I/O • 32-PIN DIP