LCC 16 PIN PACKAGE Search Results

CERAMIC LEADLESS CHIP CARRIER

Abstract: CERAMIC LEADLESS CHIP CARRIER LCC 52 PACKAGE CERAMIC LEADLESS CHIP CARRIER LCC LCC-16C-F01
Contextual Info: LEADLESS CHIP CARRIER 16 PAD CERAMIC LCC-16C-F01 EIAJ code : ∗QFN016-G-S250-1 16-pad ceramic LCC Lead pitch 50mil Package width x package length 250 × 250mil Sealing method Frit seal LCC-16C-F01 *Shape of PIN NO.1 INDEX : Subject to change without notice.

Contextual Info: p yp: v « *1 X X CY7C276 - 16Kx 16 Reprogrammable PROM Features Functional Description • The CY7C276 is a high-performance 16K-word by 16-bit CMOS PROM. It is available in a 44-pin PLCC/CLCC and a 44-pin LCC packages, and is 100% reprogrammable in w in­

AS4LC1M16

Contextual Info: AS4LC1M16 883C 1 MEG x 16 DRAM AUSTIN SEMICONDUCTOR, INC. PRELIMINARY DRAM 1 MEG x 16 DRAM 3.3V, EDO PAGE MODE, OPTIONAL EXTENDED REFRESH AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD 883 • SMD Planned 44/50-Pin SOJ/LCC/Gull Wing

0-32k

Abstract: CERAMIC PIN GRID ARRAY 120 pins 6A14
Contextual Info: £ n jS ¡^ DPV32X16A Dense-Pac Microsystems, Inc. 0 _ 32K X 16 UVEPROM PGA MODULE PRELIMINARY DESCRIPTION: The DPV32X16A is a 40-pin Pin Grid Array PGA consisting of two 32K X 8 UVEPROM devices in ceramic LCC packages surface mounted on a co-fired

Contextual Info: DPV64X16A Dense-Pac Microsystems, Inc. 64KX 16 UVEPROM PGA MODULE O PRELIMINARY DESCRIPTION: The DPV64X16A is a 40-pin Pin Grid Array PGA consisting of two 64K X 8 U VEPRO M devices in ceramic LCC packages surface mounted on a co-fired ceramic substrate with matched thermal coefficients.

CY7C276-25JC

Abstract: C276 CY7C276 CY7C276-25HC C2761 CY7C276-30JC c2762 C2767
Contextual Info: 1CY 7C27 6 CY7C276 16K x 16 Reprogrammable PROM Features Functional Description • 0.8-micron CMOS for optimum speed/power The CY7C276 is a high-performance 16K-word by 16-bit CMOS PROM. It is available in a 44-pin PLCC/CLCC and a 44-pin LCC packages, and is 100% reprogrammable in windowed packages. The memory cells utilize proven EPROM

Contextual Info: DPS8X16A Dense-Pac Microsystems, Inc. HIGH SPEED 8K X 16 CMOS SRAM PCA MODULE O PRELIMINARY DESCRIPTION: The DPS8X16A is a 40-pin Pin Grid Array PGA consisting of two 8K X 8 SRAM devices in ceramic LCC packages surface mounted on a co-fired ceramic substrate with matched thermal coefficients.

a841

Abstract: 36A6
Contextual Info: DPV128X16A □PM Dense-Pac Microsystems. Inc. ^ H IG H SPEED 128K X 16 UVEPROM PGA M O D U LE PRELIMINARY DESCRIPTION: The DPV128X16A is a 40-pin Pin Grid Array PGA consisting o f tw o 128K X 8 UVEPROM devices in ceramic LCC packages surface mounted on a co-fired

MT4C1259

Contextual Info: MT4C1259 883C 256K x 1 DRAM AUSTIN SEMICONDUCTOR, INC. DRAM 256K x 1 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883 18-Pin LCC 16-Pin DIP (D-2) 2 /W/E /R/A/S NC AD AZ MARKING • Timing 100ns access 120ns access

CY7B333

Contextual Info: I UOOO. O /O U /9 U Revision: Tuesday, December 22,1992 - CY7B333B PRELIMINARY CYPRESS " SEMICONDUCTOR General-Purpose Synchronous BiCMOS PLD • Available in 28-pin, 300-mil PDIP, cerDIP, PLCC, and LCC packages • Programmable security bit Features • 16 I/O macrocells, each having:

Contextual Info: « ~ DPV64X16A 64K X 16 UVEPROM PGA MODULE Dense-Pac Microsystems, Inc. 0 PRELIMINARY D ESC R IPT IO N : The DPV64X16A is a 40-pin Pin Grid Array (PGA consisting of two 64K X 8 U V E P R O M devices in ceramic LCC packages surface mounted on a co-fired

Contextual Info: AS4C1259 883C 256K X 1 DRAM AUSTIN SEM IC O N D U C TO R , INC. « p DRAM 256K x 1 DRAM FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883 18-Pin LCC 16-Pin DIP (D-2) FEATURES • Industry standard pinout and timing

66171-300

Abstract: 66171 K2710 4N49 Micropac* 66171
Contextual Info: 66171 PROTON RADIATION TOLERANT, QUAD CHANNEL, HERMETIC 20 PIN LCC, OPTICALLY COUPLED ISOLATOR OPTOELECTRONIC PRODUCTS DIVISION 04/16/2009 Features: Applications: • • • • • • • • • • • High Reliability Base lead provided for conventional transistor

Contextual Info: SHM-49 □MñSL High Speed, 0.01% Hybrid Sample/Hold PRELIMINARY PRODUCT DA TA MECHANICAL DIMENSIONS FEATURES • • • • 16 MHz small signal bandwidth Small 8 pin DIP or LCC package 200 nanoseconds maximum acquisition time to 0.01% 100 nanoseconds maximum sample/hold settling time

Contextual Info: A S D MT4C1259 883C 256K X 1 DRAM AUSTIN SEMICONDUCTOR, INC. D R A M 2 5 6 K X 1 D R A M FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883 18-Pin LCC 16-Pin DIP (D-2) FEATURES • Industry standard pinout and timing

AS4C1259

Abstract: ba816 CSR1010
Contextual Info: ASÍ? AUSTIN SEMICONDUCTOR, INC. 2? 9J ? ? Í : 256K X 1 DRAM 256K DRAM 1 DRAM X FAST PAGE MODE AVAILABLE AS MILITARY SPECIFICATIONS PIN ASSIGNMENT Top View • MIL-STD-883 18-Pin LCC 16-Pin DIP (D-2) FEATURES • Industry standard pinout and timing • All inputs, outputs and clocks are fully TTL

Contextual Info: IDT7MC4005 16Kx 16 CMOS STATIC RAM MODULE Integrated Device Technology, Inc. FEATURES: • High-density 256K CMOS static RAM module • Fast access time; 15ns max. • Low profile 36-pin sidebraze ceramic DSIP (Dual Single In­ line Package) • Surface mounted LCC components mounted on a co-fired

Contextual Info: DPS8X16A □PM Dense-Pac Microsystems, Inc. H IG H SPEED 8 K X 16 C M O S S R A M P G A M O D U L E O PRELIMINARY DESCRIPTIO N: The DPS8X16A is a 40-pin Pin Grid Array PGA consisting of two 8 K X 8 SR A M devices in ceramic LCC packages surface mounted on a co-fired ceramic

ac 120* phase shift circuit diagram

Abstract: VH470 AD2S80A DB10 2S81 resolver-to-digital
Contextual Info: GENERAL DESCRIPTION The AD2S80A is a monolithic 10-, 12-, 14- or 16-bit tracking resolver-to-digital converter contained in a 40-pin DIP or 44pin LCC ceramic package. It is manufactured on a BiMOS II process that combines the advantages of CMOS logic and bipolar high accuracy linear circuits on the same chip.

Contextual Info: DPS32X16A □PM Dense-Pac Microsystems, Inc. O H IG H SPEED 3 2 K X 16 C M O S S R A M P G A M O D U L E PRELIM INARY DESCRIPTIO N: The DPS32X16A is a 40-pin Pin Grid Array PGA consisting of two 32K X 8 S R A M devices in ceramic LCC packages surface mounted on a co-fired ceramic

Contextual Info: □MñEL S H M -4 9 High Speed, 0.01% Hybrid Sample/Hold PR ELIM IN A R Y PR O D U C T DATA FEATURES MECHANICAL DIMENSIONS • • • • 16 MHz small signal bandwidth Small 8 pin DIP or LCC package 200 nanoseconds maximum acquisition time to 0.01% 100 nanoseconds maximum sample/hold settling time

2S82HP

Abstract: 2S82JP resolver motor 2S80 2S82 2S82KP 2S82LP
Contextual Info: ANALOG DEVICES INC IbE D □ AN ALO G D E V IC E S FEATURES Monolithic BiMOS II Tracking R/D Converter 44-Pin J Leaded Chip Carrier (LCC) 10-, 12-, 14- and 16-Bit Resolution Set by User Ratiometric Conversion Low Power Consumption - 300mW typ Dynamic Performance Set by User

Contextual Info: D P V 128X 16A H IG H S PEED 1 2 8 K X 16 U V E P R O M P G A M O D U L E PRELIM IN ARY D ESCRIPTIO N: The DPV128X16A is a 40-pin Pin Grid Array PG A consisting of two 128K X 8 U V EP R O M devices in ceramic LCC packages surface mounted on a co-fired ceramic substrate with matched thermal coefficients.

Contextual Info: DPS88H16 16K X 8 C M O S S R AM M O D U L E NOT RECOMENDED FOR NEW DESIGNS DESCRIPTION: The DPS88H 16 is a 16K X 8 SRAM m odule b u ilt w ith eight 4K X 8 C M O S SRAMs in ceram ic LCC packages suface m ounted on a 28-pin, 0.600" w id e Co-Fired DIP substrate. The m em ory utilizes asyncronous circuitry