KM718 Search Results

Contextual Info: KM736V849 KM718V949 256Kx36 & 512Kx18 Pipelined NtRAMTM Document Title 256Kx36-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. June. 09. 1998 Preliminary 0.1 1. Changed DC parameters ICC; from 450mA to 420mA at 150MHZ.

KM718FV4011H-5

Abstract: KM718FV4011H-6 KM736FV4011H-5 KM736FV4011H-6 SA10 SA12 SA13 SA15
Contextual Info: KM736FV4011 KM718FV4011 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

KM718V787-10

Abstract: KM718V787-8 KM718V787-9
Contextual Info: PRELIMINARY KM718V787 128Kx18 Synchronous SRAM Document Title 128Kx18-Bit Synchronous Burst SRAM, 3.3V Power Datasheets for 100TQFP Revision History Rev. No. History Draft Date Remark Rev. 0.0 Initial draft Nov. 02. 1996 Preliminary Rev. 1.0 Final spec release

Contextual Info: 512Kx18 Pipelined NtRAMTM KM718V949 Document Title 512Kx18-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. June. 09. 1998 Preliminary 0.1 1. Changed DC parameters ICC; from 450mA to 420mA at 150MHZ. ISB1; from 10mA to 20mA, I SB2 ; from 10mA to 20mA.

Contextual Info: KM718V787A 128Kx18 Synchronous SRAM Document Title 128Kx18-Bit Synchronous Burst SRAM Revision History v. No. Historv Draft Date REMARK 0.0 Initial draft. Sep. 16. 1998 Prelim inary 1.0 Final spec release. Nov. 16. 1998 Final 2.0 Add Supply voltage 2.5V

ZZ 160 ITT

Abstract: 36/ZZ 160 ITT
Contextual Info: KM736S849 KM718S949 PRELIMINARY 256Kx36 & 512Kx18 Pipelined NfRAM Document Title 256KX36 & 512Kx18-Bit Pipelined NfRAM™ Revision Historv R ev. No. H isto rv Draft Date R em ark 0.0 1. Initial document. September. 1997 Prelim inary 0.1 1. Changed speed bin from 167MHz to 150MHz

Contextual Info: PRELIMINARY 256Kx18 Synchronous SRAM KM718V890 Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date 0.0 Initial draft Decmber. 15. 1997 0.1 Change speed symbol 6.0/6.7/7.5/8.5 to 60/67/75/85, February. 02. 1998

Contextual Info: KM736FV4022 KM718FV4022 PRELIMINARY 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

Contextual Info: PRELIMINARY KM718B86 64Kx18 Synchronous SRAM 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B86 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of

Contextual Info: 64Kx18 Synchronous SRAM KM718B86 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • On-Chip Address Counter. The KM718B86 is a 1,179,648 bit Synchronous Static Random Access Memory designed to support 66MHz of Intel secondary caches. It is organized as 65,536 words

Contextual Info: PRELIMINARY 128Kx18 Synchronous SRAM KM718V789A Document Title 128Kx18-Bit Synchronous Pipelined Burst SRAM BeyisionHislory Rev. No. 0.0 History Initial draft Draft Date Remark Sep. 16. 1998 Prelim inary The attached data sheets are prepared and approved by SAM S U N G Electronics. S AM SU NG Electronics CO., LTD. reserve the right to change the

KM718V849

Abstract: KM736V749
Contextual Info: KM736V749 KM718V849 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAM TM Revision History History Draft Date Remark 0.0 1. Initial document. July.06. 1998 Preliminary 0.1 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75

Contextual Info: PRELIMINARY KM718BV87AT 64Kx18 Synchronous SRAM 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION. • Synchronous Operation. • On-Chip Address Counter. • W rite Self-Timed Cycle. •On- Chip Address and Control Registers ■ Single 3.3V±5% Power Supply.

Contextual Info: KM736FV4021 KM718FV4021 PRELIMINARY 128KX36 & 256KX18 SRAM 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Draft Date Rem ark Rev. No. H istory Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

Contextual Info: 64Kx18 Synchronous SRAM KM718BV90 64K X 18-Bit Syncronous Burst SRAM FEA TU R ES G E N ER A L DESCRIPTIO N • Synchronous Operation. • On-Chip Address Counter. The KM718BV90 is a 1,179,648 bit Synchronous Static • • • • • • Intel secondary caches. It is organized as 65,536 words

Contextual Info: PRELIMINARY 64Kx18 Synchronous SRAM KM718B86 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B86 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of

Contextual Info: KM718V890 256Kx18 Synchronous SRAM Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date REMARK 0.0 Initial draft Decmber. 15. 1997 Preliminary 0.1 Change speed symbol 6.0/6.7/7.5/8.S to 60/67/75/85, Change 7.5 bin to 7.2

Contextual Info: PRELIMINARY 256Kx18 Synchronous SRAM KM718V889 Document Title 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Draft Date Rev. No. History 0.0 Initial draft M a y. 15. 1997 0.1 Change 7.5 bin to 7.2 January . 13 . 1998 0.2 Change speed symbol6.0/6.7/7.2/8.5 to 60/67/72/85

Contextual Info: KM718V889 256Kx18 Synchronous SRAM 256Kx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. - 2 Stage Pipelined Operation With 4 Burst • On-Chip Address Counter. • Self-Timed W ite Cyde. • On-Chip Address and Control Registers.

Contextual Info: KM736V990 KM718V090 PRELIMINARY 512Kx36 & 1Mx18 Synchronous SRAM Document Tills 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft 0.0 Initial draft Jan. 18. 1999 Prelim inary 0.1 1. Update ICC & ISB values. 2. Remove tCYC 1 17MHz -8 5

6n7p

Abstract: SAL3
Contextual Info: KM736FV4011 KM718FV4011 PRELIMINARY 128KX36 & 256Kx18 SRAM 128Kx36 & 256Kx18 Synchronous Pipelined SRAM FEATURES • 128KX36 or 256Kx18 Organizations. • 3.3V Core/1,5V Output Power Supply. • HSTl Input and Output Levels. • Differential, HSTL Clock Inputs K, R.

Contextual Info: KM718V895 256Kx18 Synchronous SRAM 256Kx18-Bit Synchronous Pipelined Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • 2 Stage Pipelined Operation With 4 Buret • On-Chip Address Counter. • Self-Timed Write Cyde. • On-Chip Address and Control Registers.

Contextual Info: KM736V849 KM718V949 PRELIMINARY 256Kx36 & 512KX18 Pipelined NfRAM Document Title 256Kx36 & 512Kx18-Bit Pipelined N/RAM™ Rev. No. History Draft Date Remark 0.0 1. Initial document. June. 09. 1998 Prelim inary 0.1 1. Changed DC param eters Ic c ; from 450m A to 420m A at 150MHZ.

Contextual Info: KM718B90 64Kx18 Synchronous SRAM 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B90 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of • Self-Timed Write Cycle.