128KX36 Search Results

IBM0418A41NLAB

Abstract: IBM0418A81NLAB IBM0436A41NLAB IBM0436A81NLAB
Contextual Info: IBM0436A41NLAB IBM0418A41NLAB IBM0418A81NLAB IBM0436A81NLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM . Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • Registered outputs • 30 Ω drivers

K7A401800B-QC

Abstract: K7A401809B K7A401809B-QC K7A403200B-QC K7A403209B K7A403209B-QC K7A403609B K7B401825B-QC K7B403225B-QC
Contextual Info: K7A403609B K7A403209B K7A401809B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

K7A401800B

Abstract: K7A401800B-QC K7A401809B-QC K7A403200B K7A403200B-QC K7A403209B-QC K7A403600B K7B401825B-QC K7B403225B-QC
Contextual Info: K7A403600B K7A403200B K7A401800B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

IBM0418A8ACLAB

Abstract: IBM0436A4ACLAB IBM0436A8ACLAB IBM0418A4ACLAB
Contextual Info: . IBM0418A4ACLAB IBM0436A8ACLAB Preliminary IBM0418A8ACLAB IBM0436A4ACLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology

K7N401801B

Abstract: K7N403601B
Contextual Info: K7N403601B K7N401801B 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 350mA to 290mA at -16,

CY7C1350

Abstract: IDT71V546 MCM63Z736
Contextual Info: fax id: 1103 CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V546, MT55L128L36P and MCM63Z736 • Supports 143-MHz bus operations with zero wait

IBM0418A4ANLAB

Abstract: IBM0418A8ANLAB IBM0436A4ANLAB IBM0436A8ANLAB
Contextual Info: . Preliminary IBM0418A4ANLAB IBM0418A8ANLAB IBM0436A8ANLAB IBM0436A4ANLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25µ CMOS technology • Synchronous Register-Latch Mode of Operation

IBM0418A41XLAB

Abstract: IBM0418A81XLAB IBM0436A41XLAB IBM0436A81XLAB
Contextual Info: . Preliminary IBM0418A81XLAB IBM0436A81XLAB IBM0418A41XLAB IBM0436A41XLAB 8Mb 256Kx36 & 512Kx18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 8Mb: 256K x 36 or 512K x 18 organizations 4Mb: 128K x 36 or 256K x 18 organizations • 0.25 Micron CMOS technology

7C1351-40

Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737
Contextual Info: fax id: 1102 CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states

Contextual Info: I = = = = •= Preliminary IBM0418A81QLAA IBM0418A41 QLAA IBM0436A81QLAA IBM0436A41QLAA 8Mb 256Kx36 & 512x18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 256K x 36 or 512K x 18 organizations • Registered Outputs • 128K x 36 or 256K x 18 organizations

Contextual Info: I = =• = Preliminary IBM0418A80QLAB IBM0418A40QLAB IBM0436A80QLAB IBM0436A40QLAB 8Mb 256Kx36 & 512x18 and 4Mb (128Kx36 & 256Kx18) SRAM Features • 256K x 36 or 512K x 18 Organizations • Registered Addresses, W rite Enables, Synchro­ nous Select, and Data Ins.

Contextual Info: K7N403609B K7N403209B K7N401809B 128Kx36/x32 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

Contextual Info: K7P403611M K7P401811M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

Contextual Info: K7B403625B K7B403225B K7B401825B 128Kx36/x32 & 256Kx18 Synchronous SRAM Document Title 128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Burst SRAM Revision History History Draft Date Remark 0.0 1. Initial draft May. 15. 2001 Preliminary 0.1 1. Changed DC parameters

KM718FV4011H-5

Abstract: KM718FV4011H-6 KM736FV4011H-5 KM736FV4011H-6 SA10 SA12 SA13 SA15
Contextual Info: KM736FV4011 KM718FV4011 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

CY7C1350

Contextual Info: fax id: 1103 * g S S M ^ % rrv rt n n n CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture F e a tu re s F u n c t io n a l D e s c r ip t io n • Pin compatible and functionally e q u iv a le n ts ZBT™ devices IDT71V546, MT55L128L36P and MCM63Z736

Contextual Info: K7A403600M 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft May . 15. 1997 Preliminary 0.1 Change 7.5 bin to 7.2 January . 13 . 1998 Preliminary 0.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85

SA15

Abstract: K7P401811M K7P403611M SA10 SA12 SA13
Contextual Info: K7P403611M K7P401811M 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

Contextual Info: KM736V789 128Kx36 Synchronous SRAM D o c u m e n t T itle 128Kx36-Bit Synchronous Pipelined Burst SRAM R e v is iflü - H is io r y Rev. No. History Draft Date Remark 0.0 Initial draft May . 15. 1997 Preliminary 0.1 Change 7.5 bin to 7.2 January . 13 . 1998

Contextual Info: KM736FV4022 KM718FV4022 PRELIMINARY 128Kx36 & 256Kx18 SRAM Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Preliminary specification release Rev. 0.1 - Change specification format. No change was made in parameters.

Contextual Info: KM736V787 PRELIMINARY 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Burst SRAM Revision History Rev.No. History Draft Date 0.0 Initial draft May. 15. 1997 0.1 Modify power down cycle timing & Interleaved read timing, Feb. 11.19 9 8 Remark

7C1351-40

Abstract: 7C1351-50 7C1351-66 CY7C1351 IDT71V547 MCM63Z737 DQ31-0
Contextual Info: fax id: 1102 Back CY7C1351 PRELIMINARY 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT devices IDT71V547, MT55L128L36F and MCM63Z737 • Supports 66-MHz bus operations with zero wait states

EOIZ

Contextual Info: CY7C1351 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description The CY7C1351 is a 3.3V 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the

K7N401801M

Abstract: K7N403601M
Contextual Info: K7N403601M K7N401801M 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAM TM Revision History History Draft Date Remark 0.0 1. Initial document. July.06. 1998 Preliminary 0.1 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75