K7A403600M Search Results

Contextual Info: K7A403600M 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft May . 15. 1997 Preliminary 0.1 Change 7.5 bin to 7.2 January . 13 . 1998 Preliminary 0.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85

K7A403600M

Abstract: advh
Contextual Info: K7A403600M 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 Initial draft April . 14. 1998 Preliminary 0.1 Change Undershoot spec from -3.0V pulse width ≤20ns to -2.0V(pulse width ≤ t CYC/2)

Contextual Info: K7A403600M 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 Initial draft April . 14. 1998 Preliminary 0.1 Change Undershoot spec from -3.0V pulse width≤20ns to -2.0V(pulse width≤tCYC/2)

K7A403600M

Contextual Info: K7A403600M 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft May . 15. 1997 Preliminary 0.1 Change 7.5 bin to 7.2 January . 13 . 1998 Preliminary 0.2 Change speed symbol 6.0/6.7/7.2/8.5 to 60/67/72/85

K7A403600M

Contextual Info: K7A403600M 128Kx36 Synchronous SRAM Document Title 128Kx36-Bit Synchronous Pipelined Burst SRAM Revision History History Draft Date Remark 0.0 Initial draft April . 14. 1998 Preliminary 0.1 Change Undershoot spec from -3.0V pulse width≤20ns to -2.0V(pulse width≤tCYC/2)

K7A803609B-PC25

Abstract: K7A403600B-PC16 K7I161882B-EC16 K6R4016V1D-TC08 K7A403600M-QC16 K7I161882B-EC30 K6R4008V1C-JC12 K6R4016V1D-UC10 K6R1008V1C-JC10 K7R643682M-FC20
Contextual Info: SAMSUNG # - Connect pin 14 FT pin to Vss * - Tie down extra four I/Os with resistor K6R1016V1C-FC10 K6R1016V1C-FC12 K6R1016V1C-FC15 K6R1016V1C-FC20 K6R1016V1C-JC10 K6R1016V1C-JC12 K6R1016V1C-JC15 K6R1016V1C-JC20 K6R1016V1C-TC10 K6R1016V1C-TC12 K6R1016V1C-TC15

Contextual Info: ZLAN-150 MVTX280x Memory Interface Application Note Contents April 2005 1.0 Overview 2.0 Introduction 3.0 Memory Interfaces 3.1 SBRAM Interface Signals 3.2 ZBT-SBRAM Interface Signals 3.3 Bootstrap Settings 3.4 Acceptable SBRAM Memory 3.5 Acceptable ZBT-SRAM Memory

MVTX260X

Abstract: MC8031
Contextual Info: MSAN-211 MVTX260x/ZL5041x SBRAM Memory Interface Application Note Contents March 2005 For the chipsets with GE ports MVTX2603/4 & ZL50417/8 , two memory banks are required. There is no option to disable the second bank. The FE only chipsets (MVTX2601/2 & ZL50415/6) require one bank

KM62256BLG-7

Abstract: K6R4016V1C-FI12 IS62LV1024LL-70T1 K6R4016V1C-TI10 K6R1016C1C-TC12 KM62256BLG7 MT58L32L32PT-7.5 GVT72024A8J-10L K6R4016V1C-FI10 K6R4008V1C-JC12
Contextual Info: ISSI SRAM Cross Reference Important: please read disclaimer on last page Cypress P/N ISSI P/N C7C1334-10AC IS61NW6432-8TQ C7C1334-5AC IS61NW6432-5TQ IS61NW6432-6TQ, C7C1334-7AC IS61NW6432-7TQ C7C1335-5.5AC IS61C632A-5TQ C7C1335-7AC IS61C632A-7TQ C7C1335-8.5AC