64KX18 Search Results

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

IBM0418A11NLAA

Abstract: IBM0436A11NLAA
Contextual Info: . Preliminary IBM0436A11NLAA IBM0418A11NLAA 32Kx36 & 64Kx18 SRAM Features • 32Kx36 or 64Kx18 organizations • Registered Outputs • 0.25 Micron CMOS technology • 30 Ohm Drivers • Synchronous Pipeline Mode of Operation with Self-Timed Late Write • Common I/O

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC QO-17
Contextual Info: CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V V CYPRESS 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfac­ es. All are 18 bits wide and are pin/functionally compatible to

metal case REGULATOR IC 7812 pin diagram

Abstract: CY7C4275 CY7C4285 CY7C42X5
Contextual Info: fax id: 5416 ^;aaazgg st CY7C4275 CY7C4285 PRELIMINARY ; U I F lm c b ti 32K/64Kx18 1 Meg Deep Sync FIFOs Functional Description Features H ig h-speed , low -pow er, first-in first-o u t F IF O m em o ries 32K x 18 (C Y 7 C 42 75 ) 64K x 18 (C Y 7 C 42 85 )

Contextual Info: fax id: 5416 CY7C4275 CY7C4285 32K/64Kx18 Deep Sync II FIFOs Featu res High-speed, low-power, first-in first-out FIFO memories 32K x 18 (CY7C4275) 64K x 18 (CY7C4285) 0.5 micron CMOS for optimum speed/power High-speed 100-MHz operation (10 ns read/write cycle

Contextual Info: PRELIMINARY KM718B86 64Kx18 Synchronous SRAM 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B86 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of

Contextual Info: 64Kx18 Synchronous SRAM KM718B86 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • On-Chip Address Counter. The KM718B86 is a 1,179,648 bit Synchronous Static Random Access Memory designed to support 66MHz of Intel secondary caches. It is organized as 65,536 words

CY7C4275V

Abstract: CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4275V CY7C4285V PRELIMINARY 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4275V/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC
Contextual Info: CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low voltage systems ■ High speed, low power, first-in first-out FIFO memories

EDI20180C

Abstract: EDI20181C EDI20182C EDI20183C EDI20184C EDI20185C
Contextual Info: m o EDI20180C-EDI20185C \ E le c tro n ic D e sig n s In c . 1 High Performance Synchronous SRAM 64Kx18 Monolithic High Speed Synchronous Static RAM Features The EDI20180C is a high performance, 1 megabit Synchronous Static RAM organized as 64Kx18, avail­

Contextual Info: CY7C4275 CY7C428532K/64Kx18 Deep Sync FIFOs 1CY7C4285 CY7C4275 CY7C4285 32K/64Kx18 Deep Sync FIFOs Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V CY7C42X5V-ASC
Contextual Info: CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

Contextual Info: ^EDI EDI20180C-EDI20185C Electronic Dmlgnt Inc. High Performance Synchronous SRAM ]F MMDOi 64Kx18 Monolithic High Speed Synchronous Static RAM Features The EDI20180C is a high performance, 1 megabit Synchronous Static RAM organized as 64Kx18, avail­ able in six versions.

CY7C4275

Abstract: CY7C4285 CY7C42X5
Contextual Info: 285 CY7C4275 CY7C4285 32K/64Kx18 Deep Sync FIFOs Features Functional Description • High-speed, low-power, first-in first-out FIFO memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle

Contextual Info: 64Kx18 Synchronous SRAM KM718BV90 64K X 18-Bit Syncronous Burst SRAM FEA TU R ES G E N ER A L DESCRIPTIO N • Synchronous Operation. • On-Chip Address Counter. The KM718BV90 is a 1,179,648 bit Synchronous Static • • • • • • Intel secondary caches. It is organized as 65,536 words

Contextual Info: PRELIMINARY 64Kx18 Synchronous SRAM KM718B86 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B86 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of

Contextual Info: KM718B90 64Kx18 Synchronous SRAM 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B90 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of • Self-Timed Write Cycle.

16Kx1

Abstract: sRAM CY7C4265V CY7C4285V CY7C42X5V CY7C42X5V-ASC CY7C4255V CY7C4275V o-ring D015
Contextual Info: CY7C4255V, CY7C4265V CY7C4275V, CY7C4285V 32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description • 3.3V operation for low power consumption and easy integration into low voltage systems ■ High speed, low power, first-in first-out FIFO memories

IBM0418A1ANLAA

Abstract: IBM0436A1ANLAA
Contextual Info: . IBM0418A1ANLAA IBM0436A1ANLAA 32Kx36 & 64Kx18 SRAM Preliminary Features • 32K x 36 or 64K x 18 organizations • Common I/O • 0.25µ CMOS technology • 30Ω Drivers • Synchronous Register-Latch Mode of Operation with Self-Timed Late Write • Asynchronous Output Enable and Power Down

TS 4142

Abstract: metal case REGULATOR IC 7812 pin diagram CY7C4275 CY7C4285 CY7C42X5 rs447
Contextual Info: fax id: 5416 CY7C4275 CY7C4285 PRELIMINARY 32K/64Kx18 Deep Sync FIFOs Features Functional Description The CY7C4275/85 are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the

KM718V687-8

Contextual Info: PRELIMINARY KM718V687 64Kx18 Synchronous SRAM 64Kx18 Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION. • Synchronous Operation. • On-Chip Address Counter. • Write Self-Timed Cycle. • On- Chip Address and Control Registers. • Single 3.3V± 5% Power Supply.

KM718B90

Abstract: 52-PLCC-SQ
Contextual Info: KM718B90 64Kx18 Synchronous SRAM 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • • • • • The KM718B90 is a 1,179,648 bit Synchronous Static Random Access Memory designed to support 66MHz of Intel secondary caches. It is organized as 65,536 words

KM718BV87-12

Contextual Info: PRELIMINARY 64Kx18 Synchronous SRAM KM718BV87 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. • On-Chip Address Counter. The KM718BV87 is a 1,179,648 bit Synchronous Static Random Access Memory designed to support zero wait

C1737

Abstract: KM718B90 KM718B90-10 KM718B90-9
Contextual Info: 64Kx18 Synchronous SRAM KM718B90 64K X 18-Bit Synchronous Burst SRAM FEATURES GENERAL DESCRIPTION • Synchronous Operation. The KM718B90 is a 1,179,648 bit Synchronous Static • On-Chip Address Counter. Random Access Memory designed to support 66MHz of Intel secondary caches. It is organized as 65,536 words