JS37 Search Results

BIOS 32 Pin PLCC

Abstract: DIP14 footprint JS29 EPM7032LCC44 aui isolation transformer diode js7 C3310 push button switch 2 pin BLM11P300S DRAM
Contextual Info: FEATURES: • Switched Ethernet Evaluation Board using one Galileo GT-48001A Switched Ethernet Controller • Provides switching between 8 10/20 Mbps Ethernet ports • Flexible uses - Standalone mode - Plug into PCI slot in a PC • 33MHz PCI Rev. 2.1 interface

OJ36

Abstract: EPM7032 ARXD 149 u18n JS29 74FCT163244 MAX708 R119 EDATA-10 2A1823
Contextual Info: A B C D E SRAMs TestPoints RAS*[3:0] OCAS*[3:0] ECAS*[3:0] RAS*[3:0] OCAS*[3:0] ECAS*[3:0] AD[31:0] DAdr[11:0] OData[31:0] EData[31:0] BAdrO[2:0] OWr*[3:0] dev_adr[21:0] BAdrE[2:0] EWr*[3:0] DevRD1* SramCS* OSramCS* BAdrO[2:0] AD[31:0] DAdr[11:0] BAdrE[2:0]

js83

Abstract: 28f040 JS98 edo dram 72-pin simms 64mb JS108 JS-105 74LS373SC JS31-JS32 JS107 BYU25
Contextual Info: 32-bit i960Jx Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Flexible evaluation, benchmark, software, and hardware development system for the GT-32090 System

Contextual Info: 2N3700HR Hi-Rel 80 V, 1 A NPN transistor Datasheet - production data Features BVCEO 80 V IC max 1A HFE at 10 V - 150 mA >100 1 2 3 3 3 TO-18 4 1 1 2 2 LCC-3 UB Pin 4 in UB is connected to the metallic lid Figure 1. Internal schematic diagram • Hermetic packages

RD2 TP10

Abstract: L6244 J311 PDI 40 JS29 EPM7032 JS37 4.7k j33 TXD RXD R105
Contextual Info: A B C DData[31:0] DData[31:0] DAddr[8:0] DAddr[8:0] DAddr[8:0] RAS~[1:0] WE~ CAS~ ChipSel~ RAS~[1:0] WE~ CAS~ ChipSel~ RAS~[1:0] WE~ CAS~ ChipSel~ DData[31:0] 4 Int~ Req~ Serr~ IdSel DevSel~ Stop~ Par Perr~ Frame~ IRdy~ TRdy~ Gnt~ PCI CBE~[3:0] PRst~ PciClk

Contextual Info: r = J S G S - T H O R Æ « g iii ¥ M O ( g § * 7 / M S O N T S 5 0 7 0 T S 5 0 7 1 PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION • COMPLETE CODEC AND FILTER SYSTEM INCLUDING : - TRANSMIT AND RECEIVE PCM CHANNEL FILTERS - |x-LAW OR A-LAW COMPANDING CODER

PAR64

Abstract: BAD46 JS73 FRAME32 CLK32 led par64 BAD32 RST32 CON20B CON10A-JTAG
Contextual Info: A B 64 CON BLOCK CLK[3.6] CLK[3.6] CLK3 CLK4 CLK5 CLK6 RST[3.6] RST[3.6] RST3 RST4 RST5 RST6 4 CBE[0.7] IDSEL[3.6] IDSEL[3.6] CLK32_3 CLK32_4 CLK32_5 CLK32_6 TDO[3.6] TDI[3.6] IDSEL32_[0.3] TMS REQ32_[0.3] TCK TRST CLK32_[0.3] 3 DEVSEL SERR PERR

5201/002/05R

Contextual Info: 2N3700HR Hi-Rel 80 V, 1 A NPN transistor Datasheet - production data Features 1 BVCEO 80 V IC max 1A HFE at 10 V - 150 mA >100 2 3 3 3 TO-18 4 1 1 2 2 LCC-3 UB • Hermetic packages Pin 4 in UB is connected to the metallic lid Figure 1. Internal schematic diagram

74FCT163244

Abstract: JS301 74FCT162244 JS29 MAX708 R102 R119 7032RST PCI SIZE ARXD 149
Contextual Info: A B C D E SRAMs TestPoints RAS*[3:0] OCAS*[3:0] ECAS*[3:0] RAS*[3:0] OCAS*[3:0] ECAS*[3:0] AD[31:0] DAdr[11:0] OData[31:0] EData[31:0] BAdrO[2:0] OWr*[3:0] dev_adr[21:0] BAdrE[2:0] EWr*[3:0] DevRD1* SramCS* OSramCS* BAdrO[2:0] AD[31:0] DAdr[11:0] BAdrE[2:0]

GT-64011

Abstract: 29F400 85C30 R4640
Contextual Info: Galileo-9 PCI Evaluation Platform for GT-64011 and IDT R4640 Preliminary Revision 1.1 1/19/98 - http://www.galileoT.com info@galileoT.com Tel 408 367-1400 Fax (408)367-1401 Galileo-9 PCI Evaluation Platform for GT-64011 and IDT R4640 1. Introduction The Galileo-9 PCI Evaluation Platform for GT-64011 and IDT R4640 provides embedded developers with a convenient

0/C0402X7R160-104K

Abstract: Si500S
Contextual Info: C P 2 11 4 - E K CP211 4 E VALUATION K I T U SER ’ S G UIDE 1. Kit Contents The CP2114 Evaluation Kit is available in four configurations shown in Table 1: Table 1. Evaluation Kits Kit Name Components CP2114 CP2114-EK evaluation board cable RS-232 serial cable

JANSR2N3700UB

Abstract: ESCC
Contextual Info: 2N3700HR Hi-Rel 80 V, 1 A NPN transistor Datasheet - production data Features 1 BVCEO 80 V IC max 1A HFE at 10 V - 150 mA >100 2 3 3 3 TO-18 4 1 1 2 2 LCC-3 UB • Hermetic packages Pin 4 in UB is connected to the metallic lid Figure 1. Internal schematic diagram

Contextual Info: 45E D 712*1537 G03b744 S C S -T H O M S O N m 4 ISÛTH G S-THOMSON T S 2 7 2 C ,I,M -1 9 -0 5 -zo HIGH SPEED DUAL CMOS OP-AMPs • EXCELLENT PHASE MARGIN ON CAPACI­ TIVE LOADS - SYMETRICAL OUTPUT CURRENTS ■ HIGH GAIN BANDWIDTH PRODUCT ■ LOW OUTPUT DYNAMIC IMPEDANCE

Contextual Info: HOLE HI-8020 Series INTEGRATED CIRCUITS CMOS HIGH VOLTAGE DISPLAY DRIVER GENERAL DESCRIPTION The HI-8020 high voltage display driver is a functional replacement for the AMI S5420 and Micrel MIC8013/8014 series. This CMOS product is designed to drive liquid crystal displays by

DE-A10

Abstract: SED1345 JS41 TP177 29F400 flash DEA10 act 30b equivalent SOD-17 GALILEO TECHNOLOGY procedure TP61 equivalent
Contextual Info: 64-bit R4XXX Galileo-4 Evaluation & Development Preliminary November 95, Rev. 1.0 System FEATURES • Evaluation, benchmark, software, and hardware development system - R4XXX PCI Controller adapter board - Passive PCI Backplane motherboard - Optional Galileo-2 Secondary Cache module

Contextual Info: 2N3700HR Hi-Rel 80 V, 1 A NPN transistor Datasheet - production data Features BVCEO 80 V IC max 1A HFE at 10 V - 150 mA >100 1 2 3 3 3 TO-18 4 1 1 2 2 LCC-3 UB Pin 4 in UB is connected to the metallic lid Figure 1. Internal schematic diagram • Hermetic packages

FRAME32

Abstract: bad33 CON10A-JTAG PAR64 JS47 74FCT163244CPA CLK32 JS29 JS-54 CON20B
Contextual Info: A B 64 CON BLOCK CLK[3.6] CLK[3.6] CLK3 CLK4 CLK5 CLK6 RST[3.6] RST[3.6] RST3 RST4 RST5 RST6 4 CBE[0.7] IDSEL[3.6] IDSEL[3.6] CLK32_3 CLK32_4 CLK32_5 CLK32_6 TDO[3.6] TDI[3.6] IDSEL32_[0.3] TMS REQ32_[0.3] TCK TRST CLK32_[0.3] 3 DEVSEL SERR PERR

29F400

Abstract: 85C30 R4640 74FCT163244 CON101-1
Contextual Info: alileo Galileo-9 PCI Evaluation Platform for GT-64011 and IDT R4640 Preliminary Revision 1.0 8/22/97 - www.galileoT.com info@galileoT.com Tel: +1-408.451.1400 Fax: +1-408.451.1404 Galileo Technology 1. Galileo-9 PCI Evaluation Platform for GT-64011 and IDT R4640