J-K FLIP FLOPS Search Results

DM74LS73A

Abstract: DM74LS73AM DM74LS73AN M14A MS-001 N14A
Contextual Info: Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

TTL 74109

Abstract: 8530510 74109 PIN CONFIGURATION 74109
Contextual Info: 74109, LS109A Signetics Flip-Flops Dual J-K Positive Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION T h e '1 0 9 is dual positive edge-triggered JK-type flip-flop featuring individual J, K, Clock, S e t and R eset inputs; also com ­

pin diagram of 7473

Abstract: ttl 7473 N74LS73 7473 pin diagram 74LS73 ok2t p 7473 n 74LS73 TTL 7473 Flip-Flops 7473
Contextual Info: 7473, LS73 Signetics Flip-Flops Dual J-K Flip-Flop Product Specification Logic Products DESCRIPTION The '73 is a dual flip-flop with individual J, K, C lock and direct Reset inputs. The 7473 is positive pulse-triggered. JK infor­ mation is loaded into the m aster while

Contextual Info: January 1988 MM54HCT109/MM74HCT109 Dual J-K Flip-Flops with Preset and Clear General Description These high speed J-K FLIP-FLOPS utilize advanced silicongate CMOS technology. They possess the low power con­ sumption and high noise immunity of standard CMOS inte­

Contextual Info: GD54/74LS109A DUAL POSITIVE-EDGE- TRIGGERED J-K FLIP-FLOPS Feature Pin Configuration • Positive Edge-Triggering • Direct Set and reset inputs • J and K inputs • Q and Q outputs Vcc CLR2 J2 K2 C LK 2 PR2 Q2 QS R RRRFI R HR y Description This device contains two independent positiveedge-triggered J-K flip-flops with complementary out­

Contextual Info: LS TTL DN74LS Series D N 7 4 LS1 1 2 DN74LS112 i0 7 ^ IS ¡ ¡ ^ Dual J-K Negative Edge-Triggered Flip-Flops with Set and Reset H Description P -2 DN 74LS112 contains two negative-edge triggered J-K flipflop circuits, each w ith independent clock-CP, J, K, and

Contextual Info: * SY10EL35 SY100EL35 JK FLIP-FLOP SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES • 525ps propagation delay The SY10/100EL35 are high-speed JK Flip-Flops. The J/K data enters the m aster portion of the flip-flop when the clock is LOW and is transferred to the slave and,

AS 15 -g

Abstract: LW2J
Contextual Info: TYPES SN54276, SN74276 QUADRUPLE J-K FLIP-FLOPS O C T O B E R 1 9 7 6 — R E V IS E D D E C E M B E R 1 9 8 3 features • Four J-K Flip-Flops in a Single Package . . . Can Reduce FF Package Count by 50% • Separate Negative-Edge-Triggered Clocks with Hysteresis , . . Typically 200 mV

Contextual Info: SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 • SN54ALS109A, SN54AS109A . . . J PACKAGE SN74ALS109A, SN74AS109A . . . D OR N PACKAGE TOP VIEW

54HC112

Contextual Info: SN54HC112, SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET 02684, DECEMBER 1982-REVISED SEPTEMBER 1987 SN54HC112 . . . J PACKAGE SN74HC112 . . . D OR N PACKAGE TOP VIEW ] 1CLK C 1 O l 6 H V CC i k C 2 15 3 1CLR 14 H 2CLR u [ 3

Contextual Info: gl M O T O R O L A M C74AC109 M C 74A C T109 Dual J K Positive Edge-Triggered Flip-Flop DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC74AC109/74ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. T h ejtocking operation is independent of rise and fall

Contextual Info: SN54ALS112A, SN74ALS112A DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS199A – APRIL 1982 – REVISED DECEMBER 1994 • SN54ALS112A . . . J PACKAGE SN74ALS112A . . . D OR N PACKAGE TOP VIEW Fully Buffered to Offer Maximum Isolation

Contextual Info: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW

Contextual Info: H ITA C H I/ LOGIC/ARRAYS/MEN TE D Ë | 44i h a D 3 DülDBbS 92D HD74HC108 10365 fl D Dual J-K Flip-Flops with Preset Common Clear, and Common Clock PIN ARRANGMENT T h is flip -flo p is edge sensitive to the clo c k in p u t and change state o n the negative tran sition o f the clo c k pulse. Each

MH 7472

Abstract: ic 7472 ttl 7472 ttl TTL 7472
Contextual Info: SN5472, SN7472 AND-GATED J-K M ASTER-SLAVE FLIP-FLOPS WITH PRESET AND CLEAR DECEMBER 1963 - REVISED MARCH 1988 S N 5 4 7 2 . . J P AC KA G E S N 7 4 7 2 . . . N P AC K A G E Package Options Include Plastic and Ceramic DIPs and Ceramic Flat Packages TO P VIE W

T 7411-1

Contextual Info: TYPES SN54111, SN74111 DUAL J-K MASTER-SLAVE FLIP-FLOPS WITH DATA LOCKOUT R E V IS E D DECEMBER 1983 S N 5 4 1 11 . . . J OR W PACKAGE • Package Options Include Plastic and Ceramic DIPs S N 7 4 1 11 . . . J OR N PACKAGE Dependable Texas Instruments Quality and

74HC113

Abstract: D Flip Flops
Contextual Info: SN 54H C 113. SN 74H C 113 DUAL J K NEGATIVE-EDGE-TRIGGERED FLIP FLOPS WITH PRESET D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1 9 8 7 T O P V IEW L J 14 1C LK Ü Dependable Texas Instruments Quality and Reliability 1 K L 1J C ip r e h description

Contextual Info: SN54F109, SN74F109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDFS047A- MARCH 1987 - REVISED OCTOBER 1993 • Package Options Include Plastic Smali-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs

MC891P

Abstract: MC700P MC791P tny 290 MCS91P ECTF MC891 1N3063 MC890P MC889P
Contextual Info: ^ PLA ST IC M R T L MC700P/800P series DUAL IK FUP-fLOPS M C 791P • M C 891P Tw o J -K flip -f lo p s in a s in g le p a c k a g e . E a c h flip -flo p h a s a d i r e c t c le a r i n p u t in a d d itio n t o t h e c lo c k e d in p u ts . Cl] 3 - S

Contextual Info: ADVANCE INFORMATION SN 54F114, SN 74F114 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COM MON CLEAR, AND COMMON CLOCK D2932, MARCH 1987 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

C114 e s j

Abstract: 74hc114 c114
Contextual Info: SM54HC114, SM74HC114 DUAL J-K NEGATIVE EDGE-TRIGGERED FLIP-FLOPS WITH PRESET. COMMON CLEAR. AND COMMON CLOCK D 26B4, D ECEM BER 1 9 8 2 -R E V IS E D SEPT EM B ER 1987 S N 54H C 114 . . . J PACKAGE SN 74H C114 . . . D OR N PACKAGE Package Options Include Plastic "Small

Contextual Info: SN54107, SN54LS107A, SN74107, SN74LS107A DUAL J-K FLIP-FLOPS WITH CLEAR SDLS036 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

Contextual Info: January 1988 Semiconductor MM54HC113/MM74HC113 Dual J-K Flip-Flops with Preset General Description out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static dis­ charge by internal diode clamps to V cc and ground.

Contextual Info: CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D D D D D D CD54ACT109 . . . F PACKAGE CD74ACT109 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With