IRD2 Search Results

vq80

Abstract: A40MX02 one time
Contextual Info: Revision 3 40MX and 42MX Automotive FPGA Families Features High Capacity Ease of Integration • Single-Chip Applications ASIC Alternative for Automotive • Up to 100% Resource Utilization and 100% Pin Locking • 3,000 to 54,000 System Gates • Deterministic, User-Controllable Timing

Contextual Info: User’s Manual V850E/ME2 32-Bit Single-Chip Microcontroller Hardware µPD703111A Document No. U16031EJ3V0UD00 3rd edition Date Published June 2004 N CP(K) Printed in Japan [MEMO] 2 User’s Manual U16031EJ3V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

antifuse programming technology

Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 42MX24
Contextual Info: v6.0 40MX and 42MX FPGA Families Fe a t ur es High C apaci t y • • • • • • Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages Single-Chip ASIC Alternative 3,000 to 54,000 System Gates Up to 2.5 kbits Configurable Dual-Port SRAM

79R3000

Contextual Info: RISC CPU PROCESSOR IDT79R3000A IDT79R3000AE Integrated Device Technology, Inc. FEATURES: Dynamically able to switch between Big- and Little- Endian byte ordering conventions. Coprocessor Interface— The IDT79R3000A generates all addresses and handles memory interface control for up to

TAG L7

Abstract: fpu coprocessor PR31 PR3400 PR3000A mps 1136 TAG 93
Contextual Info: PaceMips" PR3400N CPU 32-BIT RISC PROCESSOR WITH FLOATING POINT ACCELERATOR FEATURES • CPU and FPA in a monolithic VLSI package ■ 32-BIT RISC Processor PaceMips PR3000A that contains thiity-two general purpose 32-bit registers ■ On-Chip Memory Management Unit provides fast

P1rxd

Abstract: LTE repeater
Contextual Info: M ITEL NWK950 Fast-Ethernet Multiport Repeater SEMICONDUCTOR Prelim inary Inform ation DS4810 -1 .3 The NWK950 is a 4-port Fast Ethernet Repeater conforming to the IEEE 802.31 00BASE-TX Standard. The device integrates the 802.3 Repeater functions with 4 instances of the 10OBASE-X

Contextual Info: Æ ic te - m ! v 2 .0 Radiation-Hardened Field Programmable Gate Arrays Features Guaranteed Total Dose Radiation Capability Low Single Event Upset Susceptibility High Dose Rate Survivability Latch-Up Im m unity Guaranteed QML Qualified Devices

LCX017AL

Abstract: LCX023 LCX023AL CXA2112R CXD2453Q
Contextual Info: CXD2453Q Timing Generator for LCD Panels For the availability of this product, please contact the sales office. Description The CXD2453Q is a timing signal generator for driving the LCX017AL and LCX023AL LCD panels. This chip outputs timing signals which support XGA

h1f2

Abstract: LCX017 RM4 TG ym 238 220 r3d fri10 CXA2112R CXD2467Q LCX023 LCX028
Contextual Info: CXD2467Q Digital Signal Driver/Timing Generator For the availability of this product, please contact the sales office. Description The CXD2467Q incorporates digital signal processor type RGB driver and timing generator functions onto a single IC. Operation is possible with a system clock up

Contextual Info: DP83850C 100 Mb/s TX/T4 Repeater Interface Controller 100RIC General Description Features ol e te The DP83850C 100 Mb/s TX/T4 Repeater Interface Con- • IEEE 802.3u repeater and management compatible troller, known as 100RIC, is designed specifically to meet ■ Supports Class II TX translational repeater and Class I

TA138

Abstract: TA280 3SB24 TA1225A 176-CPGA dece2x4
Contextual Info: ACTEL CORP Æ Ic M b?E » I • 01^24^ DDDGÔ33 TS1 ■ ACT ACT 2 Field Programmable Gate Arrays Features Description • The ACT™ 2 family represents Actel’s second generation of field programmable gate arrays FPGAs . The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules.

ALY SMD

Abstract: 5962-9096501MUC actel a1240 176-CPGA actel 1240a 1240A ST
Contextual Info: ACTEL CORP b7E D • 0 1 = 1 2 4 ^ □ □ □ □ eì3cì 3SD ■ ACT ACT 1 and ACT 2 Military Field Programmable Gate Arrays ACT 1 Features • U p to 2000 G ate A rray G ates 6000 P L D e q u iv alen t g ates • R eplaces up to 53 T T L P ackages

Contextual Info: SONY CXD2453Q Timing Generator for LCD Panels Description The CXD2453Q is a tinning signal generator for driving the LCX017AL and LCX023AL LCD panels. This chip outputs tinning signals which support XGA signals 1024 x 768 dots and S-XGA signals (1280 x 1024 dots).

RXE9

Abstract: DP83223 DP83840A DP83850C DP83856
Contextual Info: DP83850C 100 Mb/s TX/T4 Repeater Interface Controller 100RIC General Description Features The DP83850C 100 Mb/s TX/T4 Repeater Interface Con- • IEEE 802.3u repeater and management compatible troller, known as 100RIC, is designed specifically to meet ■ Supports Class II TX translational repeater and Class I

132-PIN CERAMIC PIN GRID ARRAY CPGA

Abstract: A3265DX Actel A1240 WD109 A1225XL A1240XL A1280XL A32100DX A32140DX A32200DX
Contextual Info: Integrator Series FPGAs – 1200XL and 3200DX Familes Features Cadence, Escalade, Exemplar, IST, Mentor Graphics, Synopsys and Viewlogic • JTAG 1149.1 Boundary Scan Testing High Capacity • • • • 2,500 to 40,000 logic gates Up to 4 Kbits configurable dual-port SRAM

transistor power mx 614

Abstract: 40MX 42MX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 hp 2800 diode
Contextual Info: Preliminary Data Sheet Integrator Series FPGAs – 40MX and 42MX Families Features • Supported by Actel Designer Series development system with interfaces to popular design environments such as Cadence, Exemplar, IST, Mentor Graphics, Synopsys, Synplicity, and Viewlogic

A3200DX

Abstract: DIODE 044 1334 smd 5962-9215602MXA 5962-9552001MYC A1280XL A32100DX A32140DX 5962-9215602MYA A32300DX Resistor SMD 310
Contextual Info: HiRel Field Programmable Gate Arrays Features 3200DX • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • 100 MHz System Logic Integration • Device Sizes from 1200 to 30,000 gates • Highest Speed FPGA SRAM, up to 4 Kbits Configurable

SiS 486 schematic

Contextual Info: Accelerator Series FPGAs - ACT 3 Family Features • Replaces up to twenty 32 macro-cell CPLDs • Up to 10,000 Gate Array Equivalent Gates up to 25,000 equivalent P L IJ Gates • Replaces up to one hundred 20-pin PAL Packages • Highly Predictable Performance with 100% Automatic

RA 8040

Abstract: transistor SMD c5c phl 409 64x4 memory SMD cq 603 transistor BIM G18 Y1 smd transistor asy CQ256
Contextual Info: m e te ! v3 .0 - m 40MX and 42MX Families FPGAs F e a tu re s • QML Certification H ig h C a p a c ity • Ceramic Devices Available to DSCC SMD • Single Chip ASIC Alternative E a s e o f In t e g r a tio n • 2,000 to 36,000 Available Logic Gates

RTM 866 - 480

Abstract: saj 141 OA67 wd 969 ir 40MX04 RTM 866 - 485 kSO 947 262
Contextual Info: 40 Preliminary D ala Sheet -» Revision 1.1 I ntegr ator SeriesFP GAs: 40MX and 42MX Families Features * Deterministic, User-Controllable Timing Via DirectTime Software Tools. High C apacity * MX Diagnostics and Debug Supported by Silicon Explorer. * 2,000 to 52,000 Available Logic Gates

GP128

Abstract: IRd4 bel 5558-5999 5558-5999 ST6184 100BASE NWK954 unmanaged repeater 2047-bit TP-PMD DEVICE
Contextual Info: NWK954 QUAD FAST ETHERNET REPEATER PRELIMINARY INFORMATION Supersedes January 1998 version, DS4842 - 1.1 DS4842-2.1 April 1998 The NWK954 is a fully integrated, unmanaged, 4-port Fast Ethernet Repeater conforming to the IEEE 802.3 100BASE-TX Standard. The device integrates the 802.3 Repeater functions

Silicon Sculptor II

Abstract: 40B5 42B2 RT54SX-S TQ100 180-pin
Contextual Info: v4.3 eX Family FPGAs FuseLock Leading Edge Performance • • • • • 240 MHz System Performance 350 MHz Internal Performance 3.9 ns Clock-to-Out Pad-to-Pad • • • Specifications • • • • • 3,000 to 12,000 Available System Gates Maximum 512 Flip-Flops (Using CC Macros)

HiRel a54sx72a unused

Contextual Info: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10

rt54sx32su

Abstract: RTSX72 RTSX32SU RTSX72-S
Contextual Info: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case