IEEE1596 Search Results

DS90LV019

Abstract: DS90LV019TM DS90LV019TMTC EIA-644 IEEE1596 M14A MTC14
Contextual Info: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DS90LV019 は EIA-644 及び IEEE1596.3 SCI LVDS 規格に適 合しておりこのデバイスを 2 個使用することにより1 対 1 の低消 費、高速 100Mbps 以上 (50MHz) の全二重のデジタル伝送が構

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • • • • • • • • The PI90LVB010 is a differential line driver and receiver transceiver that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA644LVDS standards, the difference is that the driver output current

IEEE1596

Abstract: PI90LVB010 PI90LVB010U PI90LVB010UE PI90LVB010W PI90LVB010WE
Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • • • • • • • • The PI90LVB010 is a differential line driver and receiver transceiver that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA644LVDS standards, the difference is that the driver output current

IEEE1596.3

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • Bus LVDS Signaling BLVDS The PI90LVB010 is a differential line driver and receiver (transceiver) that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA• Designed for Double Termination Applications

IEEE1596.3

Abstract: IEEE1596 10MF 35V IEEE-1596 DS90LV018A DS90LV031A EIA-422 EIA-644 M08A ds90
Contextual Info: • ■ ■ ■ ■ ■ ■ ■ DS90LV018A は EIA-644 および IEEE1596.3 SCI LVDS 規格 に適合しており同規格の LVDS のドライバと組み合わせると 1 対 1 の低消費電力、高速 400Mbps (200MHz) 以上のデジタル 伝送が構成できます。

IEEE1596

Abstract: PI90LVB010 PI90LVB010UE PI90LVB010WE
Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • • • • • • • • The PI90LVB010 is a differential line driver and receiver transceiver that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA644LVDS standards, the difference is that the driver output current

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • Bus LVDS Signaling BLVDS The PI90LVB010 is a differential line driver and receiver (transceiver) that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA• Designed for Double Termination Applications

MC 4011 BCP

Abstract: PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT
Contextual Info: EtherPHAST -24 Device 2x OC-12/STM-4 SONET/SDH Ethernet Mapper TXC-06745 DATA SHEET TXC-06745-MB, Ed. 2 February 2006 FEATURES APPLICATIONS • Client Interfaces: 2x GMII/24x SMII/4x TBI/MPI 24 channel packet all pin shared • Two serial Gigabit Ethernet (1.25 Gbit/s) ports with integrated CRSU/SerDes (8B/10B)

radar detector detector 10-25 ghz

Abstract: A7- B14 Radar Warning Receiver 6 pin DCI DCI circuit diagram ADF4350 TCI-1-13M AD9129 AD9129-MIX-EBZ nsd 102
Contextual Info: Preliminary Technical Data FEATURES DAC Update Rate of up to 5.6 GSPS Direct RF Synthesis @ 2.8 GSPS Data Rate DC-to-1.4 GHz in Baseband Mode DC-to-1.0 GHz in 2x Interpolation Mode 1.4 to 4.2 GHz in Mix-Mode Bypassable 2x Interpolation Excellent Dynamic performance

IBM "embedded dram"

Abstract: m5m4v4169 Intel 1103 DRAM Nintendo64 IBM98 toshiba fet databook dynamic memory controler MOSYS eDRAM "1t-sram" MoSys
Contextual Info: ABSTRACT MODERN DRAM ARCHITECTURES by Brian Thomas Davis Co-Chair: Assistant Professor Bruce Jacob Co-Chair: Professor Trevor Mudge Dynamic Random Access Memories DRAM are the dominant solid-state memory devices used for primary memories in the ubiquitous microprocessor systems of

DS3100

Abstract: DS3105 DS3105LN GR-1244-CORE GR-253-CORE LQFP64 MCR10 ACS8525 MCR10 ROHS D1801
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing

DB01P

Abstract: DCI circuit diagram
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET AD9739 SYNC_OUT SYNC_IN LVDS DDR RECEIVER I120 CLK DISTRIBUTION DIV-BY-4 SYNCCONTROLLER TxDAC CORE IOUTP IOUTN DACCLK 07851-001 DCO VREF DLL (MU CONTROLLER) Broadband communications systems Military jammers Instrumentation, automatic test equipment

nx10 alarm system

Abstract: nx10 alarm
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3102 is a highly integrated central timing and

ADT2T-1T-1P

Abstract: AD9739 AD9739BBCZ docsis 9508g ADCLK914 593 ph 9425 ADT2T INTEL Core i7 860 AVDD33
Contextual Info: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter AD9739 FUNCTIONAL BLOCK DIAGRAM RESET SYNC_IN_P SYNC_IN_N DB0[13:0]P DB0[13:0]N DB1[13:0]P DB1[13:0]N LVDS DRIVER CLOCK DISTRIBUTION SYNCHRONIZER DCI_P DCI_N LVDS DRIVER SYNC_OUT_P SYNC_OUT_N LVDS RECEIVER

d 9329

Abstract: trc 9500 8755 interfacing chip pin diagram of ic 7489 agilent 8762 22253d IC TA 7089 P 74344 IT 8755 E j 5804 f11
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION DIV-BY-4 IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems

PEC 4179 DIODE

Abstract: 327879-001US
Contextual Info: Intel Communications Chipset 89xx Series Datasheet October 2012 Order Number: 327879-001US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

IEEE-1596

Abstract: E5430 R161 022 BAV99ZXCT LC1210 AD9734 AD9735 AD9736 AVDD33 esd p3
Contextual Info: 10-/12-/14-Bit, 1200 MSPS DACS AD9734/AD9735/AD9736 FEATURES FUNCTIONAL BLOCK DIAGRAM RESET A reduced-specification LVDS interface is utilized to achieve the high sample rate. The output current can be programmed over a range of 8.66 mA to 31.66 mA. The AD973x family is

IEEE1596

Abstract: AD9734 AD9735 AD9736
Contextual Info: 14/12/10-Bit, 1200 MSPS D/A Converters Preliminary Technical Data FEATURES • • • • • • • • • • AD9736/AD9735/AD9734 FUNCTIONAL BLOCK DIAGRAM 1.8/3.3 V Single Supply Operation AD9736 SFDR > 53 dBc to fOUT = 600 MHz AD9736 IMD > 65 dBc to fOUT = 600 MHz

Contextual Info: EtherPHAST -48 Plus Device OC-48/STM-16 SONET/SDH Ethernet Mapper TXC-06742 DATA SHEET PRODUCT PREVIEW TXC-06742-MB, Ed. 4 December 2005 FEATURES APPLICATIONS • 1x STS-48/STM-16 or 4x STS-12/STM-4 framer with TOH processing, 4x 622 LVDS line side interface

IEEE1596

Abstract: PI90LV019 PI90LV019W PI90LVT019W 50ohm resistors 0201 DOUBLE DIFFERENTIAL BUS TRANSCEIVER LVB 1.32
Contextual Info: PI90LV019 PI90LVB019 PI90LVT019

d 9329

Abstract: AD9739A-FMC-EBZ j 5804 f11 DB02P Murata 7160 trc 9500 and pin diagram of IC 7491 temperature controller using microcontroller 7107 IC vco 900 1800 mhz 6MHZ
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION DIV-BY-4 IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems

nx62

Abstract: 2ic30
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3106 Line Card Timing IC www.maxim-ic.com FEATURES GENERAL DESCRIPTION Advanced DPLL Technology ƒ Programmable PLL bandwidth:18 Hz to 400 Hz ƒ Manual Reference Switching ƒ Holdover on Loss of Input Reference

temperature controller CHB 402

Abstract: c531 diode c528 transistor pair diodes C509 s401 diode C520 A/D ROHDE SCHWARZ SMHU smd diode S7 r433 l504
Contextual Info: Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC AD9219 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB to Nyquist ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.3 LSB (typical)

RF mixer 10-1000

Abstract: AD9779 AD9779A ADL5372 AVDD33 7805 V Reg
Contextual Info: Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters AD9776A/AD9778A/AD9779A FEATURES GENERAL DESCRIPTION Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA,