IEEE1596.3 Search Results

DS90LV019

Abstract: DS90LV019TM DS90LV019TMTC EIA-644 IEEE1596 M14A MTC14
Contextual Info: • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DS90LV019 は EIA-644 及び IEEE1596.3 SCI LVDS 規格に適 合しておりこのデバイスを 2 個使用することにより1 対 1 の低消 費、高速 100Mbps 以上 (50MHz) の全二重のデジタル伝送が構

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • • • • • • • • The PI90LVB010 is a differential line driver and receiver transceiver that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA644LVDS standards, the difference is that the driver output current

IEEE1596.3

Contextual Info: PI90LVB010 Single Bus LVDS Transceiver Features Description • Bus LVDS Signaling BLVDS The PI90LVB010 is a differential line driver and receiver (transceiver) that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA• Designed for Double Termination Applications

IEEE1596.3

Abstract: IEEE1596 10MF 35V IEEE-1596 DS90LV018A DS90LV031A EIA-422 EIA-644 M08A ds90
Contextual Info: • ■ ■ ■ ■ ■ ■ ■ DS90LV018A は EIA-644 および IEEE1596.3 SCI LVDS 規格 に適合しており同規格の LVDS のドライバと組み合わせると 1 対 1 の低消費電力、高速 400Mbps (200MHz) 以上のデジタル 伝送が構成できます。

DS3100

Abstract: DS3105 DS3105LN GR-1244-CORE GR-253-CORE LQFP64 MCR10 ACS8525 MCR10 ROHS D1801
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing

DB01P

Abstract: DCI circuit diagram
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET AD9739 SYNC_OUT SYNC_IN LVDS DDR RECEIVER I120 CLK DISTRIBUTION DIV-BY-4 SYNCCONTROLLER TxDAC CORE IOUTP IOUTN DACCLK 07851-001 DCO VREF DLL (MU CONTROLLER) Broadband communications systems Military jammers Instrumentation, automatic test equipment

nx10 alarm system

Abstract: nx10 alarm
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3102 Stratum 3 Timing Card IC with Synchronous Ethernet Support www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3102 is a highly integrated central timing and

DS26C31

Abstract: IEEE1596.3 DS90C401 DS90C402 EIA-422 EIA-644 IEEE1596 5K10 tia 250v
Contextual Info: DS90C401 LVDS 2 回路入り CMOS 差動出力ライン・ドライバ 概要 特長 DS90C401は平衡伝送ラインでのデジタル・データ伝送用に設計され た Low Voltage Differential Signaling LVDS 形態の 2 回路入り CMOS 差動出力のライン・ドライバです。D S 9 0 C 4 0 1 は E I A - 6 4 4 及び

d 9329

Abstract: trc 9500 8755 interfacing chip pin diagram of ic 7489 agilent 8762 22253d IC TA 7089 P 74344 IT 8755 E j 5804 f11
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION DIV-BY-4 IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems

PEC 4179 DIODE

Abstract: 327879-001US
Contextual Info: Intel Communications Chipset 89xx Series Datasheet October 2012 Order Number: 327879-001US INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

d 9329

Abstract: AD9739A-FMC-EBZ j 5804 f11 DB02P Murata 7160 trc 9500 and pin diagram of IC 7491 temperature controller using microcontroller 7107 IC vco 900 1800 mhz 6MHZ
Contextual Info: FEATURES FUNCTIONAL BLOCK DIAGRAM RESET IRQ AD9737A/AD9739A SDIO SDO CS SCLK 1.2V SPI DAC BIAS VREF DCO DATA LATCH CLK DISTRIBUTION DIV-BY-4 IOUTN TxDAC CORE IOUTP DLL (MU CONTROLLER) DACCLK 09616-001 DB1[13:0] Broadband communications systems DOCSIS CMTS systems

nx62

Abstract: 2ic30
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3106 Line Card Timing IC www.maxim-ic.com FEATURES GENERAL DESCRIPTION Advanced DPLL Technology ƒ Programmable PLL bandwidth:18 Hz to 400 Hz ƒ Manual Reference Switching ƒ Holdover on Loss of Input Reference

temperature controller CHB 402

Abstract: c531 diode c528 transistor pair diodes C509 s401 diode C520 A/D ROHDE SCHWARZ SMHU smd diode S7 r433 l504
Contextual Info: Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC AD9219 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB to Nyquist ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.3 LSB (typical)

LM317 3.3v

Abstract: IEEE1596 IEEE1596.3-1996 LM317 LMH6555 LMV321 ADC08100 ADC081000 IEEE1596.3 IEEE-1596
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

IEEE1596

Abstract: PI90LV019 PI90LV019L PI90LV019LE PI90LV019W PI90LV019WE
Contextual Info: PI90LV019

IEEE1596.3

Abstract: nx62
Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing

Contextual Info: Preliminary. Subject to Change Without Notice. PRELIMINARY DATASHEET DS3105 Line Card Timing IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS3105 is a low-cost, feature-rich timing IC for telecom line cards. Typically the device accepts two reference clocks from dual redundant system timing

IEEE1596.3-1996

Abstract: AN10830 IEEE1596 JESD204 DAC1408D JESD204A DAC1408D650 IEEE1596.3
Contextual Info: AN10830 Interconnection between JESD204A compliant devices Rev. 01 — 27 May 2009 Application note Document information Info Content Keywords JESD204A, Data Converters, CML, LVDS, Jitter, coupling Abstract This document relates to the interconnections that are required between

IC 7106

Abstract: IC 714 ssmf ACS8520 ACS8530 DS3100 DS3100GN GR-1244 GR-253 18Hz
Contextual Info: DS3100 Stratum 3/3E Timing Card IC www.maxim-ic.com GENERAL DESCRIPTION FEATURES When paired with an external TCXO or OCXO, the DS3100 is a complete central timing and synchronization solution for SONET/SDH network elements. With two multiprotocol BITS/SSU receivers

temperature controller CHB 402

Abstract: AD9287 u504 24 AD9259 AN-835 ANSI-644 AD9219 AD9228 integrated circuit u504 3 leg
Contextual Info: Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC AD9219 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB to Nyquist ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.3 LSB (typical)

10MF 35V

Abstract: DS90LV018A DS90LV031A EIA-422 EIA-644 IEEE1596 M08A IEEE1596.3
Contextual Info: ご注意：この日本語データシートは参考資料として提供しており内容が最新でない 場合があります。製品のご検討およびご採用に際しては、必ず最新の英文デー タシートをご確認ください。

LVDS lcd receiver

Abstract: DS90C031 LVDS scsi cable IEEE1596.3 DS90C032 AN-971 IEEE1596 TR30 cable lvds
Contextual Info: ご注意：日本語のアプリケーション・ノートは参考資料として提供しており内容が 最新でない場合があります。製品のご使用に際しては、必ず最新の英文アプ リケーション・ノートをご確認ください。

pecl logic voltage levels

Contextual Info: 19-1534; Rev 1; 10/99 +3.3V, 2.5Gbps, SDH/SONET, 4-Channel Interconnect Mux/Demux ICs with Clock Generator Features ♦ +3.3V Single Supply ♦ 1.45W Power Dissipation MAX3831 ♦ 4-Channel Mux/Demux with Fully Integrated 2.488GHz Clock Generator ♦ Frame Detection Maintains Channel Assignment

d 9329

Abstract: ADF4350 h 9245 AD9739 "Controller Area Network" DBC standard 8097 microcontroller 263-35DB AD9739ABBCZ ic 9399 g
Contextual Info: 14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter AD9739A Direct RF synthesis at 2.5 GSPS update rate DC to 1.25 GHz in baseband mode 1.25 GHz to 3.0 GHz in mix mode Industry leading single/multicarrier IF or RF synthesis Dual-port LVDS data interface Up to 1.25 GSPS operation