IEEE FLOATING POINT Search Results

DSP-3201

Contextual Info: ANALOG DEVICES 32-Bit IEEE Floating-Point Chipset ADSP-3201/ADSP-3202 FEATURES Complete Chipset Implementing Floating-Point Arithmetic Fully Compatible with IEEE Standard 754 Arithmetic Operations on Three Data Formats: 32-Bit Single-Precision Floating Point

C-15

Abstract: C-16 DSP96002 DSP96002 fft
Contextual Info: APPENDIX C IEEE ARITHMETIC C.1 FLOATING-POINT NUMBER STORAGE AND ARITHMETIC C.1.1 General The IEEE standard for binary floating point arithmetic provides for the compatibility of floating-point numbers across all implementations which use the standard by defining bit-level encoding of floating-point numbers.

S2EF

Abstract: 001B 010B B461D F2N3 0b461
Contextual Info: Proving the IEEE Correctness of Iterative Floating-Point Square Root, Divide, and Remainder Algorithms Marius Cornea-Hasegan, Microprocessor Products Group, Hillsboro, OR, Intel Corp. Index words: floating-point, IEEE correctness, divide, square root, remainder

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier _ ADSP-3210 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier.

Contextual Info: ANALOG DEVICES □ 64-Bit IEEE Floating-Point Chipset ADSP-3212/ADSP-3222 FEATURES Com plete 40 MFLOPS Floating-Point Chipset M ultiplier/D ivider and ALU Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Four Data Formats: 32-Bit Single-Precision Floating-Point

m15m R2

Abstract: ADSP-21XXX architecture ADSP-21020 adsp21020kg133
Contextual Info: ANALOG ► DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution

268-5400

Abstract: weitek 268-5400-00 WTL1032 1u040 WTL1033 J1439
Contextual Info: A- B, W OODARD & AS SO C INNOVATIONS IN MICROSYSTEM TECHNOLOGY WTL1032 WTL1033 4 0 8 7 3 3 -7 3 5 3 High-Speed 32-Bit IEEE Floating Point Multiplier High-Speed 32-Bit IEEE Floating Point ALU Features A complete floating-point arithmetic solution for high-speed processors

Contextual Info: 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maxim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point ALU _ ADSP-3220 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point arithmetic and logic unit ALU .

DSP-21020

Abstract: ADSP-21020
Contextual Info: ANALOG DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLQPS Peak, 66 MFLOPS Sustained Performance

ADSP-3221

Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point ALU ADSP-3221 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point arithmetic and logic unit ALU . 1.2 Part Number.

SN74ACT8847

Abstract: ACT8847 ti 8847
Contextual Info: SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square Root in 14 Cycles

ADSP-21xxx

Abstract: TSC21020E MRF transistor 237 ADSP-2100 ADSP-21000 ADSP-21020 MRF 477 21020E
Contextual Info: TSC21020E MATRA MHS 32/40-Bit IEEE Floating-Point DSP Microprocessor Features D Superscalar IEEE Floating-Point-Processor D Off-Chip Harvard Architecture Maximizes Signal Processing Performance D 33 ns, 30 MIPS Instruction Rate, Single-Cycle Execution D 90 MFLOPS Peak, 60 MFLOPS Sustained Performance

Contextual Info: ANALOG DEVICES □ 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FE A T U R E S Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture M axim izes Signal Processing Performance 30 ns, 33.3 M IP S Instruction Rate. Single-Cycle

D-10

Abstract: D-12 D-16 DSP96002 3F800000 DSP96002 APPLICATIONS DSP96002 fft
Contextual Info: APPENDIX D D.1 FLOATING-POINT NUMBER STORAGE AND ARITHMETIC D.1.1 General The IEEE standard for binary floating point arithmetic provides for the compatibility of floating-point numbers across all implementations which use the standard by defining bit-level encoding of floating-point numbers.

DSP96002

Abstract: DSP96002 APPLICATIONS 64x32
Contextual Info: MOTOROLA SEMICONDUCTOR PRODUCT INFORMATION Order this document by: DSP96002P/D DSP96002 32-BIT IEEE FLOATING-POINT DUAL-PORT DSP The DSP96002 is a single-chip, dual port, HCMOS, low-power, general purpose IEEE floating-point Digital Signal Processor DSP that features 1024 words of data RAM (equally

Contextual Info: ANALOG DEVICES □ 64-Bit IEEE Floating-Point Chipsets FEATURES Com plete Chipsets Im plem enting Floating-Point A rithm etic: Tw o M ultiplier Options and T w o ALU Options Fully Com patible w ith IEEE Standard 754 A rithm etic Operations on Four Data Formats:

Contextual Info: in te l CHAPTER 7 FLOATING-POINT UNIT The Intel Architecture Floating-Point Unit FPU provides high-performance floating-point processing capabilities. It supports the real, integer, and BCD-integer data types and the floating­ point processing algorithms and exception handling architecture defined in the IEEE 754 and

HAI 7203

Abstract: ACT8847 74ACT8847 SN74 multiplier
Contextual Info: TEXAS INSTR LOGIC SSE D 0^1723 GQÖS7G3 7 SN74ACT8847 64-Bit Floating Point Unit • Meets IEEE Standard for Single- and DoublePrecision Formats • Performs Floating Point and Integer Add, Subtract, Multiply, Divide, Square Root, and Compare • 64-Bit IEEE Divide in 11 Cycles, 64-Bit Square

CLCC 84

Abstract: CLCC84 SAB-R2000
Contextual Info: SIEMENS AKTIENGE SE LL SC HA F 47E D Ei aSBSbQS Q05SGSS b Q S I E G SIEMENS B SAB-R201OA Microcomputer Components 32/64 Bit Floating-Point Coprocessor T -4 9 -1 7 -3 8 Features: * Full conformance with ANSI /IEEE 754-1985 * IEEE Standard for binary floating-point arithmetic1

M 3211

Abstract: Rapa SP-3211 SP3211
Contextual Info: ANALOG DEVICES High Speed 64-Bit IEEE Floating-Point Multiplier ADSP-3211 1.1 Scope. This specification covers the detail requirements for a CMOS monolithic 32-bit and 64-bit IEEE Standard 754 format floating-point multiplier. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows:

Contextual Info: ADSP-8110/ADSP-8120 ADSP-7110/ADSP-7120 ANALOG ► DEVICES Floating Point Chip Set November, 1987 IFEATURES • Complete floating point and integer processor chip set supports the ANSI/IEEE STD.754 and DEC F&G formats. ■ Four data formats 64-bit floating point

56800

Abstract: IEEE-754
Contextual Info: User Manual – 56800 Family IEEE-754 Compliant Floating-Point Library Section 1. User Guide 1.1 Introduction This document presents an implementation of floating-point arithmetic as described in [1]. The following floating-point routines for the 56800 device family are implemented see also [1] and [2] for detailed

56800E

Abstract: ieee 754
Contextual Info: User Manual – 56800E Family IEEE-754 Compliant Floating-Point Library Section 1. User Guide 1.1 Introduction This document presents an implementation of floating-point arithmetic as described in [1]. The following floating-point routines for the 56800E device family are implemented see also [1] and [2] for detailed