PMD32 Search Results

DM024

Contextual Info: ANALOG DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor □ ADSP-21020 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS 32/40-bit floating-point DSP microprocessor. 1.2 Part Number. The complete pan number per Table 1 of this specification is as follows:

Contextual Info: 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maxim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

ADSP-21xxx

Abstract: dmd20 ic tms 1000 ADSP-21XXX MEMORY ADSP-2100 ADSP-21000 ADSP-21020 TSC21020F 21020F
Contextual Info: TSC21020F Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction Atmel is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

IC top 223p

Abstract: TSC21020E
Contextual Info: TSC21020E Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

PMD4m

Abstract: pmd23 A0335 G03327 ADSP-21020 ADSP-2100 ADSP-21000 TSW161 PMD24 PMD32
Contextual Info: . ANALOG DEVICES INC OßlbBOO 0033252 5 I ¡ANA 4LE ]> -r-V9-/z-û<? IEEE Floating-Point DSP Microprocessor ANALOG DEVICES FUNCTIONAL BLOCK DIAGRAM FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance

ADSP21020BG120

Abstract: ADSP-21020
Contextual Info: BACK a FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLOPS Peak, 66 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 0.58 ms

ADSP-21xxx

Abstract: 21020F ADSP-2100 ADSP-21000 ADSP-21020 TSC21020F
Contextual Info: TSC21020F Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

ADSP-21010

Abstract: ADSp21010 MRF 277 DMD29
Contextual Info: ANALOG DEVICES FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 80 ns, 12.5 MIPS Instruction Rate, Single-Cycle Execution 37.5 MFLOPS Peak, 25 MFLOPS Sustained Performance 1024-Point Complex FFT Benchmark: 1.54 ms

tsc21020f-20sbsv

Abstract: QML-38535 TSC21020F-20MBMQ
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Made technical change in paragraph 1.3. Update boilerplate to MIL-PRF-38535 requirements. - LTG 02-05-29 Thomas M. Hess B Made technical changes in section 1.3 and table I. Add vendor CAGE F7400. Update boilerplate to MIL-PRF-38535 requirements. - LTG

ADSP-21xxx

Abstract: mrf 212 PGA223 ADSP-21000 ADSP21020 ADSP-21020 TSC21020F DMD30
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

IC top 223p

Abstract: MRF high power transistor TSC21020E 32 TSC21020E ADSP-21xxx dmd 20 mrf 212 High frequency MRF transistor MRF 238 mrf 245
Contextual Info: TSC21020E Radiation Tolerant 32/40–Bit IEEE Floating–Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices ADSP–21020 32/40–Bit Floating–Point DSP. The product is pin and code compatible with ADI

Contextual Info: ANALOG DEVICES INC bSE D ö l b ö D G 0D30fl7a TT1 D 32-Bit IEEE Floating-Point DSP Microprocessor ANALOG ► DEVICES FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 80 ns, 12.5 MIPS Instruction Rate, Single-Cycle

ADSP-21xxx

Abstract: ADSP-21000 ADSP21020 ADSP-21020 TSC21020F
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

ADSP-21xxx

Abstract: ADSP-21000 ADSP21020 ADSP-21020 TSC21020F
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

DM 024

Contextual Info: Temic TSC21020F S e m i c o n d u c t o r s Radiation Tolerant 32/40-Bit IEEE Floating-Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices A D SP-21020 32/40-B it Floating-Point DSP.

ADSP-21000

Abstract: ADSP21020 ADSP-21020 TSC21020F M 9512 FY MQFPF-256 951200201
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

4153E

Abstract: ADSP-21xxx 5962-9953901VXC TSC21020F DMD20 PMD39 mrf 174 mrf 212 ADSP-21000 ADSP21020
Contextual Info: Features • • • • • • • • • • • • • • • • • • • • • • • • • Superscalar IEEE Floating-Point-Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 50 ns, 20 MIPS Instruction Rate, Single Cycle Execution

tsc21020f-20sbsv

Abstract: smd marking code 47-16 5962-9953901VXC TSC21020F-20MBMQ qml-38535 5962-9953901QXC
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED REV SHEET REV SHEET 15 16 17 REV STATUS OF SHEETS 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 REV SHEET 10 11 12 13 14 PREPARED BY PMIC N/A Thanh V. Nguyen STANDARD MICROCIRCUIT DRAWING CHECKED BY

DSP-21020

Contextual Info: Temic TSC21020E S e m i c o n d u c t o r s Radiation Tolerant 32/40-Bit IEEE Floating-Point DSP Microprocessor Introduction TEMIC Semiconductors is manufacturing a radiation tolerant version of the Analog Devices ADSP-21020 32/40-Bit Floating-Point DSP. The product is pin and code compatible with ADI

DSP-21020

Abstract: ADSP-21020
Contextual Info: ANALOG DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution 100 MFLQPS Peak, 66 MFLOPS Sustained Performance

ADSP-21xxx

Abstract: TSC21020E MRF transistor 237 ADSP-2100 ADSP-21000 ADSP-21020 MRF 477 21020E
Contextual Info: TSC21020E MATRA MHS 32/40-Bit IEEE Floating-Point DSP Microprocessor Features D Superscalar IEEE Floating-Point-Processor D Off-Chip Harvard Architecture Maximizes Signal Processing Performance D 33 ns, 30 MIPS Instruction Rate, Single-Cycle Execution D 90 MFLOPS Peak, 60 MFLOPS Sustained Performance

DMD15

Abstract: TSC21020F PMD21 PMD32 PMD24 pmd41 Drivers 3003 PMD35 PMD47
Contextual Info: Pages 1 to 37 INTEGRATED CIRCUITS, SILICON MONOLITHIC, CMOS 32/40-BIT IEEE FLOATING POINT DIGITAL SIGNAL PROCESSOR, WITH THREE STATE OUTPUTS BASED ON TYPE TSC21020F ESCC Detail Specification No. 9512/002 Issue 3 June 2008 Document Custodian: European Space Agency - see https://escies.org

DSP-21020

Abstract: DSP21020
Contextual Info: NOV 3 m ANALOG ► DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture M axim izes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle

m15m R2

Abstract: ADSP-21XXX architecture ADSP-21020 adsp21020kg133
Contextual Info: ANALOG ► DEVICES 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FEATURES Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture Maximizes Signal Processing Performance 30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution