I1993 Search Results

Contextual Info: PRELIMINARY M IC R O N 128K SRAM MODULE X M T4LS12832 32 SRAM M ODULE 128Kx 32 SRAM LOW VOLTAGE • H ig h sp eed : 20*, 25 an d 35n s • H ig h -d en sity 5 1 2 K B d esig n • H ig h -p e rfo rm a n ce, lo w -p o w er, C M O S d o u b le-m eta l p rocess

MT4C1004

Contextual Info: ADVANCE I^ IIC R O N 8 MEG DRAM _ MODULE X M T24D836 36, 16 M E G x 18 D R A M M O D U L E 8 MEG x 36,16 MEG 18 x FAST-PAGE-MODE FEATURES PIN ASSIGNMENT Top View • Industry-standard pinout in a 72-pin single-in-line package • High-perform ance CM OS silicon-gate process

LT 543 IC pin diagram

Abstract: pin diagram of lt 542
Contextual Info: MT56C0818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM |U |C R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4K x 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIGNMENT Top View • Operates as two 4K x 18 SRAM s w ith common addresses and data; also configurable as a single

LOG RX 2 1018 IC

Abstract: LOG RX 2 1018
Contextual Info: ÎOBASE-T INTERFACE MODULES Pulse. I N T E L L I G E N T Designed for Use with Most 10Base-T Transceiver Chips S O L U T I O N S Improved EMI performance for FCC & CISPR Class B certification Designed to meet or exceed IEEE 802.3 i-1993 10Base-T specifications

f9368

Abstract: f 9368 f9368-q 9368 OS 9938 I9090 9938 G K403
Contextual Info: DRAWING MADE IN 8 6 T H IR D ANGLE P R O JEC TIO N THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION £ 2 3 4 PUB DATE LOC REVISIONS FT 22 COPYRIGHT 19YR BY AMP INCORPORATED, H A R R I S B U R G ,P A . ALL INTERNATIONAL RIGHTS RESERVED. AMP PRODUCTS MAY BE COVERED BY U.S. AND FOREIGN PATENTS AND/OR PATENTS PENDING

27c020-15

Abstract: TMS27C020 TMS27PC020 tms72
Contextual Info: TMS27C020 2 097152 BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC020 2 097152 BIT PROGRAMMABLE READ-ONLY MEMORY J PACKAGEt TOP VIEW 29 ] A14 28 ] A13 Max Access/Min Cycle Time ns ns ns ns GOäObbS 25 ] A11 24 I 5 23 ] A10 A1 [ 11 A 0[ 12 D Q 0[ 13

Contextual Info: PRELIMINARY M T4C4M 4A1/B1 4 M EG X 4 DRAM v iic n o N DRAM 4 MEG X 4 DRAM FEATURES • Industry-standard x4 pinout, timing, functions and packages • High-performance CMOS silicon-gate process • Single power supply : +5V ±10% • Low pow'er, 3mW standby; 325mW active, typical (A l

Contextual Info: MT56C3818 8K x 18, DUAL 4K x 18 CACHE DATA SRAM M IC R O N CACHE DATA SRAM SINGLE 8Kx18 SRAM, DUAL 4KX18SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 18 SRAMs with common addresses and data; also configurable as a single 8K x 18 SRAM

MT56C0816

Abstract: AW 55 IC LT 5251 80386 cache
Contextual Info: M in P n M * ^ MT56C0816 8K x 16, DUAL 4K x 16 CACHE DATA SRAM CACHE DATA SRAM SINGLE 8Kx 16 SRAM, DUAL 4Kx16 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES • Operates as two 4K x 16 SRAMs with common addresses and data; also configurable as a single 8K x 16 SRAM

I1993

Contextual Info: MT52C9010 1K x 9 FIFO |U | =R O N 1K x 9 FIFO FIFO FEATURES • • • • • • • • • • • PIN A SSIG N M E N T (Top View Very high speed: 15, 20,25 and 35ns access High-performance, low-power CMOS process Single +5V ±10% supply Low power: 5mW typ. (standby); 350mW typ. (active)