HSTL STANDARDS Search Results

JESD86

Abstract: JESD8-6 HSTL standards MAX9310 MAX9311 MAX9312 MAX9313 MAX9314 MAX9315 MAX9316
Contextual Info: Maxim > App Notes > COMMUNICATIONS CIRCUITS Keywords: HSTL, PECL, high speed, interface standards, differential HSTL, high speed transceiver logic, Jedec standard, Jedec std, differential Sep 27, 2002 APPLICATION NOTE 1752 Applying HSTL Signals to PECL Input Devices

8T33FS6221

Contextual Info: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout MC100ES6221 MC100ES6221 ECL/PECL/HSTL Clock Buffer PRODUCT DISCONTINUATION NOTICEFanout

QSP24F

Contextual Info: For technical assistance call the Microelectronics Products number on the back cover. PO U H N S General Information The HSTL Dual Terminator is designed pri­ marily for terminating bus lines in HSTL systems High-Speed-Transceiver-Logic . Resistor values have been selected so

Contextual Info: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout ECL/PECL/HSTL Clock Fanout Buffer The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.

AN1545

Abstract: MC100EP221 MC100ES6221
Contextual Info: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout ECL/PECL/HSTL Clock Fanout Buffer The MC100ES6221 is a bipolar monolithic differential clock fanout buffer.

HSTL standards

Abstract: JESD8-6 JESD86 XAPP133 HSTL class I
Contextual Info: Tech Topics High-Speed Transceiver Logic HSTL Introduction Virtex Series of FPGAs feature the Xilinx exclusive SelectI/O+ technology integrating support for 20 single-ended and differential I/O standards. HSTL is one of the single-ended I/O interfaces supported by every Virtex device, eliminating the need for external level translators

Contextual Info: CDCLVP110 www.ti.com SCAS683D – JUNE 2002 – REVISED JANUARY 2011 Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver Check for Samples: CDCLVP110 FEATURES 1 • • • • • • • • • Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock

Contextual Info: JESD204B Clock Generator with 14 LVDS/HSTL Outputs AD9528 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High performance wireless transceivers LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation

Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

857L

Abstract: SY55857L SY55857LKI SY55857LKITR
Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

SY55857L

Abstract: SY55857UKI SY55857UKITR
Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

Contextual Info: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:

857l

Abstract: SY55857L SY55857LKG SY55857LKGTR SY55857LKI SY55857LKITR SY58021U
Contextual Info: Micrel, Inc. SuperLite SY55857L SuperLite™ 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SY55857L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature:

857L

Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR DESCRIPTION FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

Contextual Info: JESD204B Clock Generator with 14 LVDS/HSTL Outputs AD9528 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High performance wireless transceivers LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Preliminary Information Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer The Motorola MC100ES6221 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems,

Contextual Info: 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. Precision Edge ® SY89327L Precision Edge SY89327L FEATURES Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML Guaranteed AC performance over temp and voltage:

SPARTAN XC2S50

Abstract: SPARTAN-II SPARTAN-II xc2s100 pq208 CS144 FG256 PQ208 TQ144 VQ100 XC2S100 XC2S15
Contextual Info: Robust Feature Set • Flexible on-chip memory Distributed and Block Memory • 4 Digital Delay Lock Loops per device Efficient chip level/ board level clock management • Select I/O Technology Interface to all major bus standards HSTL, GTL, SSTL, etc…

857L

Contextual Info: 3.3V, 2.5Gbps ANY INPUT-to-LVPECL DUAL TRANSLATOR SuperLite SY55857L FINAL FEATURES • Input accepts virtually all logic standards • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC parameters over temperature: • fMAX > 2.5Gbps 2.5GHz toggle

Contextual Info: MOTOROLA Freescale Semiconductor, Inc. Order Number: MC100ES6221/D SEMICONDUCTOR TECHNICAL DATA Freescale Semiconductor, Inc. Low Voltage 1:20 Differential ECL/PECL/HSTL Clock Fanout Buffer The Motorola MC100ES6221 is a bipolar monolithic differential clock

SY89327LMGTR

Abstract: SY55857L SY89327L SY89327LMITR
Contextual Info: Precision Edge ® SY89327L Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:

SY55857L

Abstract: SY89325LMGTR SY89327L SY89327LMITR sstl lvttl Translator microleadframe
Contextual Info: Precision Edge ® SY89327L Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel, Inc. SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage:

SY55857L

Abstract: SY89327L SY89327LMITR
Contextual Info: Precision Edge 3.3V 2.5Gbps ANY INPUT-to-LVPECL DIFFERENTIAL TRANSLATOR Micrel SY89327L Precision Edge™ SY89327L FEATURES • Input accepts virtually all logic standards: • Single-ended: SSTL, TTL, CMOS • Differential: LVDS, HSTL, CML ■ Guaranteed AC performance over temp and voltage: