HEP33 Search Results
HEP33 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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kep11Contextual Info: MC10EP33, MC100EP33 3.3V / 5V ECL B4 Divider Description Features • 320 ps Propagation Delay • Maximum Frequency > 4 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • • • • • MARKING DIAGRAMS* 8 8 8 HEP33 ALYWG G 1 SOIC−8 D SUFFIX |
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mc10ep33mc100ep33mc10/100ep33mc10ep33/d+1 | |
EP33
Abstract: HEP33 HP33 KEP33 MC100EP33 MC10EP33 MC100EP33DTG
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mc10ep33mc100ep33hep33kep33+5 | |
MC10EP33
Abstract: EP33 HEP33 HP33 KEP33 MC100EP33
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mc10ep33mc100ep33hep33kep33+4 | |
transistor k81
Abstract: SY100EP33VKG SY100EP33VZC SY100EP33VZCTR SY10EP33VKC SY10EP33VKCTR SY10EP33VZC SY10EP33VZCTR EP-33
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sy10ep33v/sy100ep33vsy10/100ep33v460psm9999-121010+9 | |
XP33
Abstract: SY100EP33V SY100EP33VZC SY100EP33VZCTR SY10EP33V SY10EP33VKC SY10EP33VZC SY10EP33VZCTR SY100EP33VKG
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sy10ep33vsy100ep33v460pssy10/100ep33v+8 | |
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Contextual Info: Precision Edge SY10EP33V SY100EP33V FINAL 5V/3.3V 4GHz, ÷ 4 PECL/LVPECL DIVIDER FEATURES • Guaranteed maximum frequency >4GHz ■ 3.3V and 5V power supply options ■ Guaranteed propagation delay <460ps over temperature ■ Wide operating temperature range: –40°C to +85°C |
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sy10ep33vsy100ep33v460pssy10/100ep33v | |
ep33
Abstract: 100EP SY100EP33V SY100EP33VZI SY10EP33V SY10EP33VZI SY10EP33VZITR
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sy10ep33vsy100ep33vsy10/100ep33vxep33v+6 | |
EP33
Abstract: HEP33 HP33 KEP33 MC100 MC100EP33 MC10EP33
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mc10ep33mc100ep33mc10/100ep33r14525+6 | |
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Contextual Info: ClockWorks SY10EP33V SY100EP33V 5V/3.3V ÷ 4 DIVIDER FEATURES DESCRIPTION The SY10/100EP33V is an integrated ÷4 divider. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to |
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sy10ep33vsy100ep33v460pssy10/100ep33v | |
KLT20
Abstract: k1648 klt22 KEL32 MC100 HEP64 KLT21 LP17 KEP32 HEP139
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and8002/dklt20k1648klt22+7 | |
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Contextual Info: Precision Edge SY10EP33V SY100EP33V FINAL 5V/3.3V 4GHz, ÷ 4 PECL/LVPECL DIVIDER FEATURES • Guaranteed maximum frequency >4GHz ■ 3.3V and 5V power supply options ■ Guaranteed propagation delay <460ps over temperature ■ Wide operating temperature range: –40°C to +85°C |
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sy10ep33vsy100ep33v460pssy10/100ep33v | |
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Contextual Info: Precision Edge SY10EP33V SY100EP33V FINAL 5V/3.3V 4GHz, ÷ 4 PECL/LVPECL DIVIDER FEATURES • Guaranteed maximum frequency >4GHz ■ 3.3V and 5V power supply options ■ Guaranteed propagation delay <460ps over temperature ■ Wide operating temperature range: –40°C to +85°C |
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460pssy10ep33vsy100ep33vsy10/100ep33v | |
motorola HEP cross reference
Abstract: EPT 4045 KPT23 motorola HEP 320 cross reference vef 202 manual KEP52 MC10EP016 HEP 801 hep51 HEP64
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br1513/dapr-2001r14525dld601+10 | |
kvt22
Abstract: KVL11 KPT23 ON Semiconductor marking k1648 KLT20 HEL16 KEL32 KEL01 xaa9646
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and8002/d12mon00232dr14525kvt22+9 | |
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MC3100EP33DTGContextual Info: MC10EP33, MC100EP33 3.3V / 5V ECL B4 Divider The MC10/100EP33 is an integrated B4 divider. The differential clock inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. |
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mc10ep33mc100ep33mc10/100ep33mc10ep33/d+1 | |
MC10EP33
Abstract: EP33 HEP33 HP33 KEP11 MC100EP33 transistor 1345 3L
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mc10ep33mc100ep33mc10/100ep33mc10ep33/d+5 | |
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Contextual Info: SY10EP33V SY100EP33V FINAL 5V/3.3V 4GHz, ÷ 4 PECL/LVPECL DIVIDER FEATURES • Guaranteed maximum frequency >4GHz ■ 3.3V and 5V power supply options ■ Guaranteed propagation delay <460ps over temperature ■ Wide operating temperature range: –40°C to +85°C |
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sy10ep33vsy100ep33v460pssy10/100ep33v | |
KEP33
Abstract: KP33
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mc10ep33mc100ep33mc10/100ep33r14525+3 | |
KP33
Abstract: 100EP33
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mc10ep33mc100ep33mc10/100ep33r14525+3 | |
A1870Contextual Info: SY10EP33V/SY100EP33V 5V/3.3V, 4GHz, ÷4 PECL/LVPECL Divider Precision Edge General Description The SY10/100EP33V is an integrated ÷4 divider. The VBB pin, an internally-generated voltage supply, is ECL Pro available to this device only. For single-ended input |
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sy10ep33v/sy100ep33vsy10/100ep33v460psm9999-121010+1 | |
KP33Contextual Info: MC10EP33, MC100EP33 3.3V / 5V ECL B4 Divider Description The MC10/100EP33 is an integrated B4 divider. The differential clock inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused |
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mc10ep33mc100ep33mc10/100ep33mc10ep33/d+1 | |
HEL16
Abstract: DEVICE MARKING CODE table onsemi marking marking code onsemi marking code onsemi Diode kel33 on semiconductor traceability marking soic HEL32 HEL12 HEL31 HEL05
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and8002/dhel16device marking code tableonsemi marking+7 | |
HEP33
Abstract: EP33 MC10EP33 MC10EP33D MC10EP33DR2
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mc10ep33320psr14153mc10ep33/d+4 | |
XP33
Abstract: SY100EP33VKGTR SY100EP33V SY100EP33VZC SY100EP33VZCTR SY10EP33V SY10EP33VKC SY10EP33VZC SY10EP33VZCTR
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sy10ep33vsy100ep33v460pssy10/100ep33v+8 | |