GATE Search Results

Contextual Info: TOSHIBA TC4030BP/BF/BFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC Tran^riRP Tran^fiRF Trzin^nRFM • ^ w » . g ■ ^ w » . f ■ 'w ■■ - - Note The JEDEC SOP (FN) is not available in TC4030B QUAD EXCLUSIVE - OR GATE Japan. TC4030B contains four circuits of exclusive OR gates. Since

toshiba p300

Abstract: kd qa
Contextual Info: INTEGRATED T O SH IB A 8 -B IT CIRCUIT TECHNICAL TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT TC74ACT299P/F/FW DATA SILICON MONOLITHIC PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR The TC74ACT299 is an advanced high speed CMOS 8-BIT PIPO SHIFT REGISTER fabricated with silicon gate and

IGBT loss calculate

Contextual Info: n j] DN-57 b U N IT R O D E Design Note Power Dissipation Considerations for the UC3726N/UC3727N IGBT Driver Pair by Mickey McClure Application Engineer Motion Control Products Optimized or driving Insulated Gate Bipolar Transis­ tors (IGBTs , the UC3726N/UC3727N IGBT driver

Contextual Info: SN5409, SN54LS09, SN54S09, SN7409, SN74LS09, SN74S09 QUADRUPLE 2-INPUT POSITIVE-AND GATES WITH OPEN-COLLECTOR OUTPUTS DECEMBER 1 9 8 3 -R E V IS E D M A R C H 1 9 8 8 Package Options Include Plastic "Sm all Outline" P ackages, Ceram ic Chip Carriers and Flat P ackages, and Plastic and Ceram ic

7408, 7404, 7486, 7432

Abstract: RF400U functional diagram of 7400 and cd 4011 ls 7404 180 nm CMOS standard cell library TEXAS INSTRUMENTS 74191 4BITS s273 buffer 74374 7408 CMOS cmos 7404
Contextual Info: TGC100 Series CMOS Gate Arrays RELEASE 3.0, REVISED JANUARY 1990 • Twelve Arrays with up to 26K Available Gates • Fast Prototype Turnaround Time • Extensive Design Support - Design Libraries Compatible with Daisy, Valid, and Mentor CAE Systems - Tl Regional ASIC Design Centers

74ALS05

Abstract: diode sy 106 diode sy 180 10
Contextual Info: TOSHIBA TENTATIVE TC74VHC05F/FN/FT TO SH IBA C M O S DIGITAL INTEGRATED CIRCUIT SILICON M O N O LITH IC TC74VHC05F, TC74VHC05FN, TC74VHC05FT HEX INVERTER OPEN DRAIN _ The TC74VHC05 is an advanced high speed CMOS INVERTER fabricated with silicon gate C2MOS technology.

Contextual Info: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to

Contextual Info: Texas Instruments TGA8300 Monolithic 2- to 18-GHz Amplifier Features • ■ ■ ■ ■ 18-dBm typical output power at 1-dB gain compression 6.5-dB gain Input and output SWR less than 2:1 Size: 0.093 x 0.064 x 0.006 inch Recessed V ^ m gate structure Description

Contextual Info: TOSHIBA TC55V2325FF-100 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 65,536 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V2325FF is a 2 ,0 9 7 ,1 5 2 bit synchronous pipelined burst SRAM that is organized as 65,536 words by 32 bits and designed for use in a secondary cache to support MPUs which have burst

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations

Contextual Info: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise

IC SN74HC

Abstract: SN74HCTOO SN74HC
Contextual Info: SN54HCT00, SN74HCT00 QUADRUPLE 2-INPUT POSITIVE NANO GATES D 3 2 4 3 , NOVEMBER 1968 Inputs are TTL-Voftage Compatible S N 54H C T00 S N 74H C T00 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

T500mA

Contextual Info: TD62107F BIPOLAR DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TD62107F DARLINGTON DRIVER WITH ENABLE_ The T D 6 2 1 0 7 F is c omprised of four NPN d a rlington output stages and enable inputs w h i c h can gate the outputs. All o u t p u t s feature integral c lamp diodes for s w i t c h ­

marking 3G

Contextual Info: TC4S01F TO SHIBA C MOS DIGITAL INTEGRATED C IR C U IT SILICO N M ONOLITHIC 2 INPUT NOR GATE Unit in mm + 0.2 23-0.3 The TC4S01F is 2-input positive logic NOR gates. + 0.2 Gate output w ith in v e rte r buffer im proves the 16 input-output ch arac te ristic s and if th e load

A9RV

Abstract: 5s a315 A327
Contextual Info: TOSHIBA TC514900AJLL-70/80 524,288 WORD X 9 BIT DYNAMIC RAM DESCRIPTION The TC514900AJLL is the new generation dynamic RAM organized 524,288 word by 9 bit. The TC514900AJLL utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit

74LS27 truth table

Contextual Info: TOSHIBA TC74HC27AP/AF/AFN TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC27AP, TC74HC27AF, TC74HC27AFN Note The JEDEC SOP (FN) is not available in Japan. TRIPLE 3 -IN P U T NOR GATE The TC74HC27A is a high speed CMOS 3-INPUT NOR GATE fabricated with silicon gate C2MOS technology.

TC74HC113

Contextual Info: TC74HC113P/F TC74HC113 P /F DUAL J - K F L IP FLOP WITH CLEAR The TC74HC113 is a high speed CMOS DUAL J—K FLIP FLOP fabricated with silicon gate C 2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintain­ ing the CMOS low power dissipation.

Contextual Info: TOSHIBA TC74ACT32 Quad 2-Input OR Gate Features: • High Speed: tpcJ = 4.5ns typ. at V cc = 5V • Low Power Dissipation: lcc = 4 |iA (max.) at Ta = 25°C • Com patible with T T L Outputs: V,L = 0 .8 V (max.) V ih = 2 .0 V (min.) • Symmetrical Output Impedance: ll0Hl = I0 l = 2 4 m A

TC74HC4022

Abstract: TC74HC4022P
Contextual Info: TC74HC4022P/F TC74HC4022P/F OCTAL COUNTER/DIVIDER The TC74HC4022 is a high speed CMOS OCTAL COUNTER/DIVIDER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

54256AP

Abstract: TC54256AF 54256a TC54256P 54256AF tmm23256p 27256D tc54256ap
Contextual Info: TOSHIBA TC54256AP/AF SILICON STACKED GATE CMOS 32,768 WORD x 8 BIT ONE TIME PROGRAMMABLE READ ONLY MEMORY D e s c rip tio n The TC54256AP/AF is a 32,768 word x 8 bit one time programm able read only m em or/ m olded in a 28-pin plastic package. The TC54256AP/AF’s access time is 200ns and it has a low power standby m ode which reduces the power dissipation without

logic diagram of 7432

Abstract: Texas Instruments TTL 7432
Contextual Info: SN5432, SN 54LS32, SN54S32. SN7432, SN74LS32, SN74S32 QUADRUPLE 2-INPUT POSITIVE-OR GATES DECEMBER 1983-REVISED MARCH 1988 Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs • SN 5432. SN 54LS32, SN 54S 32 . . . J OR W PACKAGE

74ALS8003

Contextual Info: TYPES SN54ALS8003, SN74ALS8003 DUAL 2-INPUT POSITIVE-NAND GATES D 2 7 4 6 . JU LY 1 9 8 3 -R E V IS E D DECEMBER 1 9 8 3 • Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs. S N 54A LS 8003 . . . JG PACKAGE

Contextual Info: SN54LS15, SN54S15, SN74LS15, SN74S15 TRIPLE 3 INPUT POSITIVE AND GATES WITH OPEN-COLLECTOR OUTPUTS A P R IL 1 9 8 5 — R E V IS E D M A R C H Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic

th50vsf1400

Abstract: BA30
Contextual Info: TOSHIBA TH 50VSF1400/1401ACXB TENTATIVE TOSHIBA MULTI CHIP INTEGRATED CIRCUIT SILICON GATE CMOS SRAM A N D FLASH M E M O R Y M IX E D M U LTI-C H IP PACKAGE DESCRIPTION The TH50VSF1400/1401ACXB is a mixed containing a package 2,097,152-bit SRAM and a 16,777,216-bit flash memory. The SRAM is organized as 262,144 words by 8 bits and the flash memory