FCT88915 Search Results

Contextual Info: Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • 0.5 MICRON C M O S Technology • Input frequency range: 10MHz - f2Q Max. spec (FREC LSEL = HIGH) • Max. output frequency: 150MHz • Pin and function com patible with FCT88915T, M C88915T

fct88915

Abstract: PY 55
Contextual Info: FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE LOW SKEW PLL-BASED CMOS CLOCK DRIVER FCT88915TT 55/70/100/133 DESCRIPTION: FEATURES: The FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock

fct88915

Abstract: IDT74FCT88915TT MC68040 MC88915 88915TT
Contextual Info: FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE LOW SKEW PLL-BASED CMOS CLOCK DRIVER FCT88915TT 55/70/100/133 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec FREQ_SEL = HIGH

ansi y14.5m-1982 .xxxx

Abstract: diode chn 115
Contextual Info: :nW J d t In te g ra te d D e v ic e T e c h n o lo g y , Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE) FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz - f2Q Max. spec (F R E Q S E L = HIGH) • Max. output frequency: 150MHz

CHN 530

Abstract: chn 707 hiab chn 445 CHN 455
Contextual Info: :Q§ LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE : jdfr/ Integrated De vice Technology, Inc. FEATURES: FCT88915TT 55/70/100/133 mance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting in essentially

74FCT388915T

Abstract: FCT388915T MC88915T
Contextual Info: IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE Integrated Device Technology, Inc. IDT54/74FCT388915T 70/100/133/150 PRELIMINARY FEATURES:

FCT388915T

Abstract: IDT74FCT388915T MC88915T 74FCT388915
Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER 3-STATE COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) FEATURES: IDT74FCT388915T 70/100/133/150 DESCRIPTION: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec

FCT388915T

Abstract: IDT74FCT388915T MC88915T 75mhz
Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER 3-STATE COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) FEATURES: IDT74FCT388915T 70/100/133/150 DESCRIPTION: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec

79x15

Contextual Info: HIGH-SPEED 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM Features: ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6/7/9/12/15ns max. – Industrial: 12ns (max.)

TCD-1

Contextual Info: HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM IDT709279/69S/L Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12/15ns max.

388915T

Contextual Info: 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE Integrated Device Technology, Inc. FEATURES: IDT54/74FCT388915T 70/ 100/ 133/150 PRELIMINARY is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of

Contextual Info: IDT709189/79L HIGH-SPEED 64/32K x 9 OBSOLETE PARTS SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns max.

Contextual Info: HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT709169/59L Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9ns max.

Contextual Info: IDT709379/69L HIGH-SPEED 32/16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns max.

A14L

Abstract: IDT709269
Contextual Info: HIGH-SPEED 32/16K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM IDT709279/69S/L Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12/15ns max.

388915T

Abstract: 20PF FCT388915T IDT74FCT388915T MC88915T SO28-7
Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE IDT74FCT388915T 70/100/133/150 FEATURES: DESCRIPTION: − − The FCT388915T uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low

cc 3053 diode

Contextual Info: LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • 0.5 M IC R O N C M O S Technology • Input frequency range: 10M Hz - f2Q Max. spec (FR E Q _S EL = HIGH) • Max. output frequency: 133M H z • Pin and function compatible with M C 88915T

diode cc 3053

Abstract: cc 3053 diode cc 3053 st074
Contextual Info: In te g ra te d D e v ic e T e c h n o lo g y, In c . LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • • • • • • • • • • • IDT54/FCT88915T 55/70/100/133 PRELIMINARY essentially zero delay across the device. The PLL consists of

Contextual Info: HIGH-SPEED 16/8K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9ns max. Industrial: 7.5ns (max.)

A14L

Abstract: IDT709369
Contextual Info: IDT709379/69L HIGH-SPEED 32/16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 6.5/7.5/9/12ns max.

Contextual Info: ggTN y 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE IDT54/74FCT388915T 70/100/133/150 PRELIMINARY Integrated D e\ Ic e Technology, Inc« FEATURES: • > • • • • • • • • • • • 0.5 MICRON CMOS Technology Input frequency range: 10MHz - f2Q Max. spec

IC-2565

Abstract: T3054
Contextual Info: LOW SKEW PLL-BASED CMOS CLOCK DRIVER IDT54/FCT88915 55/70/100/133 PRELIMINARY Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of

FCT388915T

Abstract: IDT74FCT388915T MC88915T
Contextual Info: IDT74FCT388915T 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER 3-STATE COMMERCIAL TEMPERATURE RANGE 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) IDT74FCT388915T 70/100/133/150 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec

Power Filter Oscilator

Abstract: IDT74FCT88915TT MC68040 MC88915 74fct88915
Contextual Info: FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE LOW SKEW PLL-BASED CMOS CLOCK DRIVER FCT88915TT 55/70/100/133 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec FREQ_SEL = HIGH