C88915 Search Results

Contextual Info: Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH 3-STATE FEATURES: • 0.5 MICRON C M O S Technology • Input frequency range: 10MHz - f2Q Max. spec (FREC LSEL = HIGH) • Max. output frequency: 150MHz • Pin and function com patible with FCT88915T, M C88915T

toko rcl

Abstract: 380HB-221K 380LB-1 ADI1762 FN55 MC68040 MC88915 MC88915FN55 MC88915FN70 Nippon capacitors
Contextual Info: Order this data sheet by M C88915/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA C88915 Low Skew CMOS PLL Clock Driver The C88915 Clock Driver utilizes phase-locked loop tech­ nology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution

SE-B3

Contextual Info: AP-703 i l î t è l APPLICATION NOTE DRAM Controller for 33 MHz i960 CA/CF Microprocessors February 2, 1995 I Order Number: 272627-001 1-459 AP-506 REVISION HISTORY Changes from Rev 001 to Rev 002 include: Section Description AC TIMING Two paragraphs added after the first:

IC-2565

Abstract: T3054
Contextual Info: LOW SKEW PLL-BASED CMOS CLOCK DRIVER IDT54/74FCT88915 55/70/100/133 PRELIMINARY Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C 88915 Low S kew CMOS PLL Clock Driver The C88915 Clock Driver utilizes phase-locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock