EP610 APPLICATION Search Results

EP610

Abstract: EP610-30 altera ep610 EP610-Z5 FLIPFLOP SCHEMATIC 74HC EP610-25 EP610-35 MOPE EP610-40
Contextual Info: HIGH PERFORMANCE 16 MACROCELL EPLD FEATURES CONNECTION DIAGRAM CLKl 3 n I/O Q 10[3 3 i/O □ i/o QT 3 3 3 3 3 3 3 i/o^ I/O J j j I/O Q I/O £9 1/0 0 i/o [ 0 INPUT ^ GNO ^ O EP610 The Altera EP610 Programmable Logic Device is capable of implementing over 600 equivalent gates of

npld610

Abstract: NPLD610-10 PALCE610 EP610 ORDERING PLD610 DPLD610-25 intel 85C060 85C060 TNPLD610 intel PLD
Contextual Info: in tj ¡PLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDa • * m - m r ' "< ^ . *. » • tpQ 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Ice = 105 m A max-@ 1 MHz

85c060

Abstract: intel iPLD610 pld610 P85C060-25 D85C060-15 EP610 ORDERING intel 85C060 intel PLD 29045 EP610 "pin compatible"
Contextual Info: in tJ . ¡PLD610/85C060 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tPD 10 ns, 100 MHz C ounter Frequency w /ln tern al Feedback ■ Extensive Softw are and Programming

Contextual Info: Ml intpl 6 1992 ÌPLD610 FAST 16-MACROCELL CMOS PLD Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs • tpo 10 ns, 100 MHz Counter Frequency w/lnternal Feedback ■ Extensive Software and Programming Support via Intel and Third Party Tools

Contextual Info: intel MILITARY ¡PLD610 16-MACROCELL CHMOS juPLD Function, Pin, and JEDEC Compatible with 5C060, EP600, EP610, EP630 and CE630 PLDs Programmable Clock System with 2 Synchronous Clocks and Asynchro­ nous Clocking Option on all Registers tpD 15 ns, 66 MHz Counter Frequency

EP610-30

Abstract: EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
Contextual Info: EP610 EPLD Features * • ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tP D as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

Signal Path Designer

Contextual Info: Classic EPLD Family J a n u a ry 1998. ver. Features Data Sheet 4 * • ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features EP610 EP610I EP910 EP910I EP1810 300 450 900 Macrocells 16 24 48 Maximum user I/O pins 22 38 64 Feature Usable gates Altera Corporation

EP61Q-15

Abstract: EP61B EP610-30 EP610-35 EP610-25 EP610 EP610-15 EP610-20 EP6101-10 EP610I
Contextual Info: EP610 EPLD Features • ■ ■ ■ ■ ■ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs

P85C060-25

Abstract: D85C060 PLD610-25 D85C060-25 intel 85C060 D85C060-15 IPLD610-15 EP610 ORDERING p85c060 N85C060-12
Contextual Info: INTEL CORP tIEMORY/PLD/ in t e l SbE D • HfiSblTb D077infl fl3£ ^p ÌPLD610/85C060 FAST 16-MACROCELL CMOS PLD h ITL2 ^ '^ - o 0 Function, Pin, and JEDEC Compatible with EP600, EP610, EP610A, EP630, PALCE610,85C060 and 5C060 PLDs ■ tpo 10 ns, 100 MHz Counter Frequency

EP610

Abstract: Altera September 1991 EP610-20 acht30
Contextual Info: altera M7E D corp 05^5375 ODDgPbb T lg W ALT EP610 EPLDs High-Performance 16-Macrocell Devices Data Sheet September 1991, ver. 2 □ □ Features □ □ □ □ □ □ □ □ □ General Description H igh-density replacem ent for TTL and 74HC w ith up to 600 gates

EP610-XXT

Abstract: altera ep610 EP610-25t EP610T P610T EP610
Contextual Info: □ Features □ □ □ □ □ High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD = 15 ns Counter frequencies up to 83 MHz Pipelined data rates up to 83 MHz Programmable 1/O architecture with up to 20 inputs or 16 outputs Pin-, function-, and programming file-compatible with Altera's EP610,

EP610

Abstract: ep600i EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I
Contextual Info: EP610 EPLD H igh-perform ance, 16-macrocell Classic EPLD Com binatorial speeds with t PD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Program mable I /O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

pin configuration of ic 7483

Abstract: pin diagram for IC 7483 altera ep910i EP610I
Contextual Info: / 7 \| H i-fczi d / 7 \ /A j U I □ rv À \ Application Brief 100 March 1995, ver. 3 Introduction Understanding Classic, MAX 5000 & MAX 7000 Timing Altera devices provide device perform ance that is consistent from sim ulation to application. Before program m ing a device, you can

application of ic 7483

Abstract: ic 7483 full adder ic 7483 7483 IC 4 bit full adder EP610 EPM5032 EPM5064 EPM5128 EPM5130 EPM5192
Contextual Info: June 1996, ver. 1 Introduction Understanding MAX 7000, MAX 5000 & Classic Timing Application Note 78 Altera devices provide performance that is consistent from simulation to application. Before programming a device, you can determine the worstcase timing delays for any design. You can calculate propagation delays

P610T

Contextual Info: AN b rVa\ LI IJ LI □ J □ □ □ LI □ H igh-d en sity re placem ent for T T L and 74 H C with up to 600 gates H ig h -p e rfo rm an ce 16-m acrocell E P L D w ith tPD = 15 ns and counter frequencies up to 83 M H z Z ero -p o w e r operation 20 |iA standby

EP610

Abstract: altera ep610 AX2022 537e EP610-15 EP6101-10 EP610I
Contextual Info: E P 610 E P L D Features High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as low as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 100 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 Clock pins

fxz 556

Abstract: EP6101-10 EP610 pipelined adder EP610-Z5 EP610-30 EP610-35 EP610-25 EP610-15 EP610-20
Contextual Info: EP6 1 0 EPLD High-performance, 16-macrocell Classic EPLD Combinatorial speeds with tPD as fast as 10 ns Counter frequencies of up to 100 MHz Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins

ep610

Abstract: EP610-30 EP610-35 EP610-25 EP610-15 EP610-20 EP610I P6101
Contextual Info: EP610EPLD Features H igh -perform an ce, 16-m acrocell Classic EPLD C om binatorial speeds w ith as low as 10 ns C oun ter frequencies of up to 100 M H z Pipelined d ata rates of up to 125 M H z Program m able I / O arch itectu re w ith up to 20 inputs o r 16 ou tp uts

P6102

Abstract: EP6101-10
Contextual Info: Classic EPLD Family J a n u ary 1998. v er. J Features Data S h e e t • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family w ith logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogram m ing w ith advanced, non-volatile

FC SUFFIX altera

Contextual Info: Classic EPLD Family Data Sheet M arch 1995, ver. 2 Features • ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Classic Device Features Feature EP22V10 EP22V10E EPB10 EP610T EP610I EP910 EP910T EP910I EP1810 EP1810T Available gates 400 600 600 900 900 1,800 Usable gates

ep910 programmer

Abstract: EP610 programmer EPLD EP610-25 EP1810 EP610-15 EP610-20 EP610-30 EP910 K925
Contextual Info: Classic EPLD Family May 1999, ver. 5 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Complete device family with logic densities of 300 to 900 usable gates see Table 1 Device erasure and reprogramming with non-volatile EPROM configuration elements

EP610-25

Abstract: programmer EPLD EP1810 EP610 EP910 ep910 programmer QLCC 24 EP6101-10
Contextual Info: Classic E P L D F a m ily Ja n u a ry 1098, ve r 4 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ C om plete device fam ily w ith logic densities o f 300 to 9 X usable gates (see Table 1) D evice e ra su re an d reprogram m ing w ith advanced, non-volatile

7483 adder/subtractor

Abstract: ic 7483 full adder ttl 7483 FULL ADDER of IC 7483 7483 full adder 7483 adder
Contextual Info: Understanding MAX 5000 & Classic Timing January 1998, ver. 2 Introduction A pplication Note 78 Altera devices provide performance that is consistent from simulation to application. Before programming a device, you can determine the worstcase timing delays for any design. You can calculate propagation delays

ic 7483 full adder

Abstract: application of ic 7483 7483 IC 7483 adder ic 7483 adder ttl 7483 FULL ADDER ic 7483 ttl 7483 of IC 7483 7483 IC 4 bit full adder
Contextual Info: May 1999, ver. 3 Introduction Understanding MAX 5000 & Classic Timing Application Note 78 Altera® devices provide performance that is consistent from simulation to application. Before programming a device, you can determine the worstcase timing delays for any design. You can calculate propagation delays