EMRS 42 Search Results

em6ab160

Abstract: EM6AB160TSA EM6AB160TSA-5G DQ11 EM6AB160TS
Contextual Info: EtronTech EM6AB160TSA 32M x 16 bit DDR Synchronous DRAM SDRAM Etron Confidential Features • • • • • • • • Fast clock rate: 200MHz Differential Clock CK & CK Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture

AN-100

Abstract: CPC7582BC EIA-481-2 J-STD-020A 5510P
Contextual Info: CPC7584 Line Card Access Switch Description • Small 16-pin SOIC or micro-leadframe package • Micro-leadframe package MLP printed circuit board footprint is 70% smaller than 4TH generation EMRs and 60% smaller than SOIC version • Monolithic IC reliability

EM6A9160TSA-5G

Abstract: EM6A9160TSA EM6A9160 em6a9160ts em6a916
Contextual Info: EtronTech EM6A9160TSA 8M x 16 DDR Synchronous DRAM SDRAM Etron Confidential Features • • • • • • • • Fast clock rate: 200MHz Differential Clock CK & CK input Bi-directional DQS DLL enable/disable by EMRS Fully synchronous operation Internal pipeline architecture

ca10 switch

Abstract: EM42AM1684RTA edo ram 16Mx16
Contextual Info: 256Mb DDR SDRAM Ordering Information EM 42 AM 16 8 4 R T A – 75 L EOREX MEMORY EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : Power S : Standard L : Low power 40 41 42 43 46 48 Package F : Pb-free G: Green Density 32M : 32 Mega Bits 16M : 16 Mega Bits

Contextual Info: ESM T M14D5121632A 2C DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V 0.1V, VDDQ = 1.8V 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

M14D1G166

Abstract: m14d1g M14D1G1664A m14d1g16 DDRII esmt
Contextual Info: ESMT M14D1G1664A 2D 7DDR II SDRAM 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

Contextual Info: ESM T M14D5121632A 2H Operation Temperature Condition (TC) -40°C~95°C DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V 0.1V, VDDQ = 1.8V 0.1V VDD = 1.75V ~ 1.9V, VDDQ = 1.75V ~ 1.9V (for speed grade -1.8) Internal pipelined double-data-rate architecture; two data access per clock cycle

Contextual Info: ESMT M14D5121632A 2H Operation Temperature Condition (TC) -40°C~95°C DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z VDD = 1.75V ~ 1.9V, VDDQ = 1.75V ~ 1.9V (for speed grade -1.8) z

Contextual Info: ESM T M14D2561616A DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features JEDEC Standard VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V Internal pipelined double-data-rate architecture; two data access per clock cycle Bi-directional differential data strobe DQS, DQS ; DQS can be disabled for single-ended data strobe operation.

M14D2561616A

Abstract: DDR-533
Contextual Info: ESMT M14D2561616A Operation Temperature Condition TC -40°C~95°C DDR II SDRAM 4M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z Internal pipelined double-data-rate architecture; two data access per clock cycle

EDE5108AJSE-6E-E

Abstract: EDE5104AJSE EDE5104AJSE-8E-E EDE5108AJSE EDE5116AJSE ELPIDA DDR2 SDRAM
Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR2 SDRAM EDE5104AJSE 128M words x 4 bits EDE5108AJSE (64M words × 8 bits) EDE5116AJSE (32M words × 16 bits) Specifications Features • Density: 512M bits • Organization  32M words × 4 bits × 4 banks (EDE5104AJSE)

EDE1108AASE

Abstract: EDE1108AASE-5C-E EDE1108AASE-6E-E EDE1104AASE EDE1104AASE-4A-E EDE1104AASE-5C-E EDE1104AASE-6E-E
Contextual Info: DATA SHEET 1G bits DDR2 SDRAM EDE1104AASE 256M words x 4 bits EDE1108AASE (128M words × 8 bits) Description Features The EDE1104AASE is a 1G bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 8 banks. The EDE1108AASE is a 1G bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 8 banks.

EDE5108AHBG

Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR2 SDRAM EDE5108AHBG 64M words x 8 bits EDE5116AHBG (32M words × 16 bits) Specifications Features • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDE5108AHBG) ⎯ 8M words × 16 bits × 4 banks (EDE5116AHBG)

EDE1104AASE

Abstract: EDE1104AASE-4A-E EDE1104AASE-5C-E EDE1104AASE-6C-E EDE1108AASE
Contextual Info: PRELIMINARY DATA SHEET 1G bits DDR2 SDRAM EDE1104AASE 256M words x 4 bits EDE1108AASE (128M words × 8 bits) Description Features The EDE1104AA is a 1G bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 8 banks. The EDE1108AA is a 1G bits DDR2 SDRAM organized

EDE5104GBSA

Abstract: EDE5104GBSA-5A-E EDE5108GBSA EDE5116GBSA
Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR-II SDRAM EDE5104GBSA 128M words x 4 bits EDE5108GBSA (64M words × 8 bits) EDE5116GBSA (32M words × 16 bits) Description Features The EDE5104GB is a 512M bits DDR-II SDRAM organized as 33,554,432 words × 4 bits × 4 banks.

EDE5116AHSE

Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR2 SDRAM EDE5108AHSE 64M words x 8 bits EDE5116AHSE (32M words × 16 bits) Specifications Features • Density: 512M bits • Organization ⎯ 16M words × 8 bits × 4 banks (EDE5108AHSE) ⎯ 8M words × 16 bits × 4 banks (EDE5116AHSE)

EDE1108ACSE

Abstract: EDE1116ACSE
Contextual Info: DATA SHEET 1G bits DDR2 SDRAM EDE1104ACSE 256M words x 4 bits EDE1108ACSE (128M words × 8 bits) EDE1116ACSE (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization ⎯ 32M words × 4 bits × 8 banks (EDE1104ACSE) ⎯ 16M words × 8 bits × 8 banks (EDE1108ACSE)

NT5TU32M16BG-3C

Abstract: nt5tu64m8be 128 MB DDR2 SDRAM Nanya nt5tu32m16bg3c NT5TU32M16BG NTC 2.5D -15 NT5TU128M4BE-3C
Contextual Info: NT5TU128M4BE NT5TU64M8BE NT5TU32M16BG 512Mb DDR2 SDRAM B-Die Features • 1.8V ± 0.1V Power Supply Voltage 2k page size for x16 • 4 internal memory banks • Data-Strobes: Bidirectional, Differential • Programmable CAS Latency: 3, 4, 5, and 6 • Strong and Weak Strength Data-Output Driver

DDR2-400

Abstract: HYB18T512160AC-5 HYB18T512400AC HYB18T512400AC-5 HYB18T512800AC HYB18T512800AC-5 600 DKZ
Contextual Info: D a t a S h e e t , V 1. 0 8 , A u g . 2 0 0 3 HYB18T512400AC HYB18T512800AC HYB18T512160AC 5 1 2 M b i t D D R 2 SD R A M Memory Products N e v e r s t o p t h i n k i n g . Edition 2003-08-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

HY5PS12821

Abstract: DDR400 bt 2323 m
Contextual Info: HY5PS1G421 L M HY5PS1G821(L)M 1Gb DDR2 SDRAM(DDP) HY5PS1G421(L)M HY5PS1G821(L)M This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

Contextual Info: V59C1512 404/804/164 QB*I 512 Mbit DDR2 SDRAM, INDUSTRIAL TEMPERATURE 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 25A 25 DDR2-400 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns Clock Cycle Time (tCK4)

EDE1116AJBG-8E-F

Contextual Info: DATA SHEET 1G bits DDR2 SDRAM EDE1108AJBG 128M words x 8 bits EDE1116AJBG (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization  16M words × 8 bits × 8 banks (EDE1108AJBG)  8M words × 16 bits × 8 banks (EDE1116AJBG)

Contextual Info: PRELIMINARY V59C1512 404/804/164 QB HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 25A 25 DDR2-400 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns

V59C

Contextual Info: PRELIMINARY V59C1512 404/804/164 QC HIGH PERFORMANCE 512 Mbit DDR2 SDRAM 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 8Mbit X 16 (164) 5 37 3 25A 25 DDR2-400 DDR2-533 DDR2-667 DDR2-800 DDR2-800 Clock Cycle Time (tCK3) 5ns 5ns 5ns 5ns 5ns