DQ41R Search Results

dm38

Abstract: DM25L F1020 DQ35L0 DM31
Contextual Info: Pin Information for the Stratix II EP2S130 Device Version 2.2 Note 1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0

DM47L

Abstract: aw7 diode EP2S180 F1020 DM55L DM31T DM18B DM17B DM52L DM25L
Contextual Info: Pin Information for the Stratix II EP2S180 Device Version 2.2 Note 1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0

BE5L

Abstract: CYD18S18V18 CYD09S36V18 CYD18S36V18 SKR 175 FullFlex36
Contextual Info: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with Single Data Rate SDR operation on each port

FullFlex36

Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

FullFlex36

Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 4 Mbit, 9 Mbit, and 18 Mbit devices

DM13B

Abstract: DM15B EP2S90 F1020 DM11R DM10B DQ10B2 DQ15B2 DQ32L2
Contextual Info: Pin Information for the Stratix II EP2S90 Device Version 2.4 Note 1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2

BE5L

Abstract: CYD04S72V CYD09S72V CYD18S72V DQ60L
Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation

be5l

Contextual Info: CYD04S72V CYD09S72V CYD18S72AV FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit

FullFlex36

Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

FullFlex36

Abstract: CYDXXS36V18 400 OHM RESISTOR DQ67
Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

DQ12-DQ15

Abstract: CYDXXS36V18 16-SD FullFlex36
Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port

be5l

Abstract: CYD18S72V-133BBI CYD04S72V CYD09S72V CYD18S72V
Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit

FullFlex36

Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

0c002

Abstract: BE5L CYD18S72V-100BBC BE4L
Contextual Info: PRELIMINARY FLEx72TM 18-Mb 256K x 72 Synchronous Dual-Port RAM Seamless Migration to Next-Generation FLEx72-ETM 18-Mb Dual-Port (CYD18S72V18) Features FLEx72TM (CYD18S72V) • True dual-ported memory allows both ports to simultaneously read from the same memory location

BE5L

Abstract: 0C002
Contextual Info: CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V18-Mb 256K x 72 Synchronous Dual-Port RAM CYD18S72V FLEx72TM 18-Mb (256K x 72) Synchronous Dual-Port RAM Features FLEx72TM (CYD18S72V) • True dual-ported memory allows both ports to simultaneously read from the same memory location

be5l

Contextual Info: CYD04S72V CYD09S72V CYD18S72AV FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72™ family includes 4-Mbit, 9-Mbit and 18-Mbit

FullFlex36

Abstract: DQ67L CYD18S72V18
Contextual Info: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

Contextual Info: CYD09S72V CYD18S72V FLEx72 3.3 V 128 K/256 K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 9-Mbit, and 18-Mbit devices

FullFlex36

Abstract: CYD04S36V18 CYD09S36V18 CYD18S18V18 CYD18S36V18
Contextual Info: FullFlex FullFlexTM Synchronous SDR Dual Port SRAM FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

FullFlex36

Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR

CYD18S18V18-200BBAXI

Abstract: FullFlex36 CYD36S18V18-167BGXI
Contextual Info: FullFlex FullFlex Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access to the shared array from each port ■ Synchronous pipelined operation with single data rate SDR operation on each port

Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation

be5l

Abstract: CYD04S72V CYD09S72V CYD18S72V
Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation