DQ67L Search Results
DQ67L Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
BE5L
Abstract: CYD18S18V18 CYD09S36V18 CYD18S36V18 SKR 175 FullFlex36
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be5lcyd18s18v18cyd09s36v18cyd18s36v18+2 | |
FullFlex36Contextual Info: PRELIMINARY FullFlex Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) operation on each port |
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36-gb/s484-ball256-ballfullflex72+6 | |
FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR |
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cydxxs72v18cydxxs36v18cydxxs18v1818-mbit+4 | |
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Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 4 Mbit, 9 Mbit, and 18 Mbit devices |
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cyd04s72vcyd09s72vcyd18s72vflex72+2 | |
BE5L
Abstract: CYD04S72V CYD09S72V CYD18S72V DQ60L
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cyd04s72vcyd09s72vcyd18s72vflex72tm+5 | |
be5lContextual Info: CYD04S72V CYD09S72V CYD18S72AV FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location The FLEx72 family includes 4-Mbit, 9-Mbit and 18-Mbit |
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cyd04s72vcyd09s72vcyd18s72avflex72tm+6 | |
FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR |
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cydxxs72v18cydxxs36v18cydxxs18v1818-mbit+4 | |
FullFlex36
Abstract: CYDXXS36V18 400 OHM RESISTOR DQ67
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Original |
cydxxs72v18cydxxs36v18cydxxs18v1818-mbit+6 | |
DQ12-DQ15
Abstract: CYDXXS36V18 16-SD FullFlex36
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18-mbit36-mbitcydxxs36v18cydxxs18v18+7 | |
be5l
Abstract: CYD18S72V-133BBI CYD04S72V CYD09S72V CYD18S72V
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Original |
cyd04s72vcyd09s72vcyd18s72vflex72tm+6 | |
FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR |
Original |
cydxxs72v18cydxxs36v18cydxxs18v1872-bit+3 | |
CYD18S72V-133BBI
Abstract: CYD04S72V CYD09S72V CYD18S72V BE6R DQ49L
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cyd04s72vcyd09s72vcyd18s72vflex72tm+7 | |
0c002
Abstract: BE5L CYD18S72V-100BBC BE4L
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flex72tm18-mbcyd18s72v133-mhz+7 | |
BE5L
Abstract: 0C002
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cy7c093794vcy7c093894vcy7c09289vcy7c09369v+7 | |
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FullFlex36
Abstract: DQ67L CYD18S72V18
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Original |
18-mbit36-mbitfullflex7272-bit+3 | |
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Contextual Info: CYD09S72V CYD18S72V FLEx72 3.3 V 128 K/256 K x 72 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation ■ Family of 9-Mbit, and 18-Mbit devices |
Original |
cyd09s72vcyd18s72vflex72k/256+2 | |
FullFlex36
Abstract: CYD04S36V18 CYD09S36V18 CYD18S18V18 CYD18S36V18
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Original |
72-bit484-ball256-ballfullflex72+9 | |
FullFlex36Contextual Info: CYDXXS72V18 CYDXXS36V18 CYDXXS18V18 FullFlex Synchronous SDR Dual Port SRAM FullFlex™ Synchronous SDR Dual Port SRAM Features Functional Description • True dual port memory enables simultaneous access the shared array from each port ■ Synchronous pipelined operation with single data rate SDR |
Original |
cydxxs72v18cydxxs36v18cydxxs18v1872-bit+3 | |
CYD18S18V18-200BBAXI
Abstract: FullFlex36 CYD36S18V18-167BGXI
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fullflex7272-bitcyd18s18v18-200bbaxifullflex36+1 | |
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Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation |
Original |
cyd04s72vcyd09s72vcyd18s72vflex72tm+3 | |
be5l
Abstract: CYD04S72V CYD09S72V CYD18S72V
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Original |
cyd04s72vcyd09s72vcyd18s72vflex72tm+4 | |
FullFlex36
Abstract: CYD09S36V18 CYD18S18V18 CYD18S36V18
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Original |
72-bit18-mbit36-mbitfullflex36+3 | |
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Contextual Info: CYD04S72V CYD09S72V CYD18S72V FLEx72 3.3 V 64 K/128 K/256 K x 72 Synchronous Dual-Port RAM Functional Description Features • True dual-ported memory cells that allow simultaneous access of the same memory location ■ Synchronous pipelined operation |
Original |
cyd04s72vcyd09s72vcyd18s72vflex72tm+3 | |
FullFlex36Contextual Info: PRELIMINARY FullFlex72, FullFlex36, and FullFlex18 Synchronous DDR Dual-Port SRAM Features • True dual-ported memory allows simultaneous access to the shared array from each port • Synchronous pipelined operation with selectable Double Data Rate DDR or Single Data Rate (SDR) |
Original |
fullflex72fullflex36fullflex1836-gb/s+5 | |