DQ17D Search Results

Contextual Info: ÏÂ TOSHIBA { DI SCRET E/ OP TO } 9097250 TOSHIBA DISCRETE/OPTO D e J t DT7SS0 DQ17DQÔ □ | 99D 17008 TLRI I I GaP RED LIGHT EMISSION FEATURES: • Slim Mini Glass Sealed Type* • Small Package & Wide Viwing Angle - Suitable for Compact Equipment as a Operating

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT PD48288209, 48288218, 48288236 288M-BIT Low Latency DRAM Common I/O Description The μPD48288209 is a 33,554,432-word by 9 bit, the μPD48288218 is a 16,777,216 word by 18 bit and the μPD48288236 is a 8,388,608 word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology

Contextual Info: PRELIMINARY PDM34089 3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter Features n n n n n n n n n n n n n n n Interfaces directly with the x86, Pentium , 680X0 and PowerPC™ processors Single 3.3V power supply Mode selectable for interleaved or linear burst:

PU3119

Abstract: PU4119 ci 55 PU3219 PU4219 PU4419 PU4519
Contextual Info: Power Transistor Arrays PU3119, PU4119, PU4419 P U 3119, P U 4119, P U 4419 P ackage Dimensions PU3119 Silicon NPN Triple-Diffused Planar Type 20. 5max. Pow er Amplifier, Switching C om plem entary Pair with P U 3 2 1 9 , P U 4 21 9, P U 4 5 1 9 ° * i. jdnnpw

Contextual Info: ISSI IS61SF6436 64Kx 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION JUNE 1998 FEATURES DESCRIPTION • Fast access times: 8.5 ns, 9 ns, 10 ns The IS S I IS61SF6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: IS 6 1 C 6 3 2 A m s 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM MAY 1998 FEATURES DESCRIPTION • Fast access time: The I S S I IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: 64K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION MARCH 1997 FEATURES DESCRIPTION • Fast access times: 8 .5 ns, 9 ns, 10 ns • Internal self-tim ed write cycle • Individual Byte W rite Control and Global W rite • Clock controlled, registered address, data and

Contextual Info: IS61C632A m i 32K x 32 SYNCHRONOUS PIPELINED STATIC RAM SEPTEMBER 1997 FEATURES DESCRIPTION • The I S S I IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: 64K x 32 LOW VOLTAGE SYNCHRONOUS PIPELINE STATIC RAM ADVANCE INFORMATION MARCH 1997 FEATURES DESCRIPTION • Fast access time: The IS S I IS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: m IS61LV6432 64Kx 32 SYNCHRONOUS PIPELINE STATIC RAM i FEBRUARY 1998 FEATURES DESCRIPTION • Internal self-timed write cycle The IS S IIS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: m IS61SP6436 64Kx 36 SYNCHRONOUS PIPELINED STATIC RAM i PRELIM IN A R Y DECEM BER 1997 FEATURES • Internal self-timed write cycle DESCRIPTION • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium or linear burst sequence control

Contextual Info: IS ffl 32K x 32 SYNCHRONOUS FAST STATIC RAM PRELIMINARY JUNE 1997 FEATURES DESCRIPTION • Fast access tim e: The ISSI IS61C632A is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: issr IS61SF6432 64Kx 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION JUNE 1998 FEATURES DESCRIPTION • Fast access time: 9 ns, 10 ns The I S S I IS61SF6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

IS61S6432

Contextual Info: ISSI IS61S6432 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM JUNE 2001 FEATURES DESCRIPTION • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium or linear burst sequence control using

Contextual Info: CY7B131 CY7B141 F# CYPRESS IK x 8 Dual-Port Static RAM Features Functional Description • 0.8-micron BiCMOS for high perform ance • Automatic power-down • M aster CY7B131 easily expands data bus width to 16 or more bits using slave CY7B141 • BÜ5Ÿ output flag on CY7B131; BUSŸ

Contextual Info: m IS 61S P 6436 64Kx 36 SYNCHRONOUS PIPELINED STATIC RAM i ADVANCE INFORMATION SEPTEMBER 1997 FEATURES DESCRIPTION • Internal self-timed write cycle The I S S I IS61SP6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: ISSI IS61SF6436 64K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION MARCH1997 FEATURES DESCRIPTION • Fast access times: 8.5 ns, 9 ns, 10 ns The IS S IIS61SF6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: ISSI IS61SP6436 64Kx 36 SYNCHRONOUS PIPELINED STATIC RAM PRELIMINARY DECEMBER 1997 FEATURES DESCRIPTION • Internal self-timed write cycle The IS S IIS61SP6436 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the i486 , Pentium™,

Contextual Info: IC61S6432 Document Title 64K x 32 Pipelined Sync. SRAM Revision History Revision No History Draft Date Remark 0A Initial Draft September 13,2001 The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

W3DG6417V-D2

Contextual Info: White Electronic Designs W3DG6417V-D2 PRELIMINARY* 128MB - 16Mx64, SDRAM UNBUFFERED FEATURES DESCRIPTION PC100 and PC133 compatible The W3DG6417V is a 16Mx64 synchronous DRAM module which consists of four 16Mx16 SDRAM components in TSOP II package and one 2K EEPROM

CY7C1381B-100AI

Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B
Contextual Info: 381B CY7C1381B CY7C1383B 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion

6ao1

Contextual Info: IB M 1 1 M 3 2 7 3 5 B IB M 1 1 M 3 2 7 3 5 C 32M x 72 DRAM MODULE Features • 168 Pin JEDEC Standard, 8 Byte Dual ln-line Memory Module • 32Mx72 Dual Bank Extended Data Out Mode DIMM • Performance: • System Performance Benefits: - Buffered inputs (except RAS, Data)

Contextual Info: ISSI IS61SF632A 32K x 32 SYNCHRONOUS FLOW-THROUGH FAST STATIC RAM FEATURES • Fast access time: 9 ns, 10 ns • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium or linear burst sequence control

DQ45-A

Abstract: 033J1
Contextual Info: IBM13N1649NC IBM13N1809NC 1M x 64/80 1 Bank Unbuffered SDRAM Module Features • 168-Pin JEDEC Standard, Unbuffered 8-Byte Dual In-Line Memory Module • 1Mx64/80 Synchronous DRAM DIMM • Performance: i. CAS Latency : fcK I Clock Frequency itcK i Clock Cycle