680X0 Search Results

Contextual Info: PRELIMINARY PDM34089 3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter Features n n n n n n n n n n n n n n n Interfaces directly with the x86, Pentium , 680X0 and PowerPC™ processors Single 3.3V power supply Mode selectable for interleaved or linear burst:

Contextual Info: 64K x 32 LOW VOLTAGE SYNCHRONOUS PIPELINE STATIC RAM ADVANCE INFORMATION MARCH 1997 FEATURES DESCRIPTION • Fast access time: The IS S I IS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: m IS61LV6432 64Kx 32 SYNCHRONOUS PIPELINE STATIC RAM i FEBRUARY 1998 FEATURES DESCRIPTION • Internal self-timed write cycle The IS S IIS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: issr IS61SF6432 64Kx 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM ADVANCE INFORMATION JUNE 1998 FEATURES DESCRIPTION • Fast access time: 9 ns, 10 ns The I S S I IS61SF6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: ISSI IS61SP12832 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION MARCH 1998 FEATURES DESCRIPTION • Internal self-timed write cycle TheIS S IIS61SP12832 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: m t IS61SP25618 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION MAY 1998 FEATURES DESCRIPTION • Internal self-timed write cycle TheIS S IIS61SP25618 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: ISSI IS61LV6464 64Kx 64 SYNCHRONOUS PIPELINE STATIC RAM ADVANCE INFORMATION SEPTEMBER 1997 FEATURES DESCRIPTION • Fast access time: The IS S IIS61LV6464 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: Pa r a d ig m PDM44068 64K x 18 Fast CMOS Synchronous Static SRAM with Linear Burst Counter and Output Register Features Description □ Interfaces directly with the Motorola 680X0 and PowerPC processors 100, 80, 6 0 ,5 0 MHz □ High Speed Clock Rates

351N

Contextual Info: Paradigm PDM34078 3.3V 32K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register Features Description □ Interfaces directly with the x86, Pentium , 680X0 and PowerPC™ processors 100, 80, 66, 60, 50 MHz □ Single 3.3V power supply

MB86964

Abstract: eDP timing control VESA CIP 8D Decoder "aui transformers" SQFP100 100-PIN BA10 BA11 BA12 FPT-100-M05
Contextual Info: FUJITSU MB86964 ETHERNET CONTROLLER WITH 10BASE-T TRANSCEIVER PRELIMINARY DATA SHEET FEATURES Fully compliant with ISO/ANSI/IEEE 8802-3 specifica­ tions Provides generic interface to industry-standard micropro­ cessor busses X86, 680X0 and RISC High-performance packet-buffer architecture pipelines

T1IG

Abstract: IS61LV6432 D2259
Contextual Info: ISSP 64K x 32 LOW VOLTAGE SYNCHRONOUS PIPELINE STATIC RAM ADVANCE INFORMATION MARCH 1997 FEATURES DESCRIPTION • The IS S IIS61LV6432 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, high­ performance, secondary cache for the Pentium , 680X0™,

Contextual Info: PRELIMINARY PDM34088 3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register Features n n n n n n n n n n n n n n n n Interfaces directly with the x86, Pentium , 680X0 and PowerPC™ processors 100, 80, 66, 60, 50 MHz Single 3.3V power supply

Contextual Info: Par ad ig m PDM44066 32K x 36 Fast CMOS Synchronous Static SRAM with Linear Burst Counter and Output Register Features □ Interfaces directly with the Motorola 680x0 and PowerPC processors 100, 80, 60, 50 MHz □ High Speed Clock Rates 10.12.5.15.20 ns

Contextual Info: Paradigm PDM44036 32K x 36 Fast CMOS Synchronous Static SRAM with Linear Burst Counter Features Description n Interfaces directly with the Motorola 680X0 and PowerPC processors 80,66, 60, 50,40 MHz □ High Speed Access Times - Clock to data valid times:

Contextual Info: IS61SP25618 256K x 18 SYNCHRONOUS PIPELINED STATIC RAM ADVANCE INFORMATION MAY 1999 FEATURES DESCRIPTION • Internal self-timed write cycle Th e lS S I IS61SP25618 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Contextual Info: m IS 6 1 S P 1 2 8 3 2 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM i ADVANCE INFORMATION JUNE 1998 FEATURES DESCRIPTION • Internal self-timed write cycle The lS S I IS61SP12832 is a high-speed, low-power synchro­ nous static RAM designed to provide a burstable, highperformance, secondary cache for the Pentium , 680X0™,

Signal Path Designer

Abstract: 47 HAP1 HA20
Contextual Info: TFB2022 FUTUREBUS+ DATA PATH UNIT OCTOBER 1990 - REVISED JANUARY 1993 * Parallel-Protocol Support is Fully Compliant to Futurebus* Standard IEEE Std 896.1-1991 * Interfaces Easily to a Variety of Popular Microprocessors Such as SPARC , 680x0, 88xxx, and 80x86

MB86701

Abstract: MB86960APF-G MB86703 etherstar 10BASE BD10 BD12 BD13 BD15 MB86960
Contextual Info: MB86960 NETWORK INTERFACE CONTROLLER with ENCODER/DECODER NICE DATA SHEET FEATURES • Complies with international standards for Ethernet, ISO/ANSI/IEEE 8802-3 • Provides generic interface industry–standard microprocessor busses (x86, 680x0, RISC) • 20 Mbyte/second data transfer rate to/from the system

Contextual Info: Paradigm PDM44538 32K x 18 Fast CMOS Synchronous Static RAM with Linear Burst Counter Features Description Interfaces directly with the Motorola 680x0 and PowerPC microprocessors 80,66, 60, 50 MHz The PDM44538 is a 589,824 bit synchronous random access memory organized as 32,768 x 18 bits. It has

Contextual Info: ADVANCE INFORMATION P a r a u g m PDM34076 ' 32K x 36 Fast CMOS Synchronous Static SRAM with Burst Counter and Output Register Features Description □ Interfaces directly with the i486 , Pentium™, 680X0 and Power PC™ processors 66.6, 50,40 MHz The PDM34072 is a 1,048,576 bit synchronous ran­

Contextual Info: _ ADVANCE INFORMATION Paradigm 3.3V 32K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register Features Description □ Interfaces directly with the i486 , Pentium™, 680X0 and Power PC™ processors 66.6,50,40 MHz The PDM34072 is a 1,048,576 bit synchronous ran­

Contextual Info: ISSI IS61S6432 64K x 32 SYNCHRONOUS FAST STATIC RAM PRELIMINARY JANUARY 1997 FEATURES DESCRIPTION • The IS S IIS61S6432 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-perfor­ mance, secondary cache for the Pentium , 680X0™, and

Contextual Info: paradigm PDM34078 3.3V 32K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register Features Description □ Interfaces directly with the x86, Pentium , 680X0 and PowerPC™ processors 100, 80, 66, 60, 50 MHz □ Single 3.3V power supply

Contextual Info: paradigm ' P R E L IM IN A R Y PDM34088 3.3V 64K x 32 Fast CMOS Synchronous Static RAM with Burst Counter and Output Register Features Description □ Interfaces directly with the x86, Pentium , 680X0 and PowerPC™ processors 100, 80, 66, 60, 50 MHz □ Single 3.3V power supply