DQ14C Search Results

1MD45

Abstract: cy17 High-Zt11-12 CY10 CY82C691 CY82C692 CY82C693 DQ23P cy82
Contextual Info: PRELIM INARY CY82C692 W CYPRESS Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence

Contextual Info: IBM14N1372 IBM14N3272 IBM14N6472 High Perform ance SRAM Modules Features • 256K, 512K, and 1MB secondary cache module family using Synchronous and Asynchronous SRAMs. • Organized as a 32K, 64K, or 128K x 72 package on a 4.3” x 1.1”, 160-lead, Dual Read-out DIMM

Contextual Info: JÊL S» 1993 ADVANCE M IC R O N I .w r ^ w . ^ MT58LC64K18B2 64K x 18 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 64Kx 18 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns

Contextual Info: JIH s e 1993 ADVANCE M IC R O N I 64K SEMICONDUCTOR HC SYNCHRONOUS SRAM MT58LC64K18P3 18 SYNCHRONOUS SRAM X 6 4 K x 18 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND OUTPUTS FEATURES • • • • • • • • • • • • Fast access times: 7 , 10 ,12 and 15ns

TAA 611 T12

Abstract: x48 chipset IDT72T6360 IDT72T6480 D25N3
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

BQ4025

Abstract: bq4025Y
Contextual Info: bq4025/bq4025Y BENCHM ARQ 256Kx16 Nonvolatile SRAM Features General Description ► D ata retention in th e absence of power The CMOS bq4025 is a nonvolatile 4,194,304-bit static RAM organized as 262,144 w ords by 16 bits. The in teg ral control circuitry an d lith ­

Contextual Info: = = = = = = PreMmlnäry IB M 0 4 1 8 1 3 P Q K 64K X 18 B U R S T P I P E L I N E S R A M Features • 64K x 18 Organization • Registered Addresses, Data Ins, Control sig­ nals, and Outputs • 0.5fi CMOS Technology • Asynchronous Output Enable • Synchronous Burst Mode ot Operation Compati­

Contextual Info: HY UN DA I 64K X HY6718100/101 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x 18 SRAM core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge

Contextual Info: •HYUNDAI HY67V16100/101 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge

Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 36 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

M27C4002

Abstract: M27V402 Q0-Q15
Contextual Info: ¿ = 7 S C S -TH O M S O N ^ 7# » EfflD g[Hì(Q lIiL[|(gTniì(o)l] Ì M27V402 LOW VOLTAGE 4 Megabit (256K x 16) UV EPROM and OTP EPROM PRELIMINARY DATA i LOW VOLTAGE READ OPERATION: 3V to 5.5V FAST ACCESS TIME: 120ns LOW POWER ’’CMOS” CONSUMPTION:

BYS 045 v 72

Abstract: Aderesse
Contextual Info: SHARP LHF80S08 r-v =— . r .1/ LH28F800SU R-10 8 Mbit 512 Kbit x 16,1 Mbit x 8 5V Single Voltage Flash Memory CONTENTS PAGE CONTENTS PAGE 1.0 INTRODUCTION. 3 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS. 10

TAA 611 T12

Abstract: 72T6480 BA1-B11 d25n3 BA0-C11 k4h561638f A11-C10 q35t Q35T1 A7D9
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

Contextual Info: HY51V18165B Series •HYUNDAI 1M X 16-bit CMOS DRAM with Burst EDO PRELIMINARY DESCRIPTION The HY51V18165B is the new generation and fast dynamic RAM organized 1,048,576 x 16-bit. The HY51V118165B utilized Hyundai's C M O S silicon gate process technology as well as advenced circuit techniques

Contextual Info: JUL S 9 1983 ADVANCE llilll— p n M I MT58LC64K18A6 64Kx 18 SYNCHRONOUS SRAM SYNCHRONOUS 64K x 18 SRAM g n r tlV I + 3 -3V SUPPLY, FULLY REGISTERED I/O AND LINEAR BURST COUNTER QR AM FEATURES • • • • • • • • • • • • • Fast access times: 7,10,12 and 15ns

Contextual Info: SGS-THOMSON M27V402 R f f lD ^ [ llL liO T IjîO ll i LOW VOLTAGE _ 4 Megabit 256K x 16 UV EPROM and OTP EPROM PRELIMINARY DATA • LOW VOLTAGE READ OPERATION: 3V to 5.5V ■ FAST ACCESS TIME: 120ns ■ LOW POW ER ’’CMOS” CONSUMPTION:

Contextual Info: unir n «i nim ii i mui i iiiij.j.m u i.HHiHnj; MICRON TECHNOLOGY INC b lllS H T 3flE D QG0SÖ73 S • MRN ADVANCE T 'H L -2Z - H 16K x 16 SRAM SRAM WITH A D D R E SS / DATA INPUT LATCHES a FEATURES • • • • • • • • • PIN A SSIG N M EN T Top View)

Contextual Info: HY6718110/111 HYUNDAI 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a

72T6480

Abstract: dsc-6358 IDT72T6360 IDT72T6480 D2312
Contextual Info: 2.5V SEQUENTIAL FLOW-CONTROL DEVICE 48 BIT WIDE CONFIGURATION For use with 128Mb to 256Mb DDR SDRAM FEATURES • IDT Standard mode or FWFT mode of operation • Empty and full flags for monitoring memory status • Programmable Almost-Empty and Almost-Full flags, each flag

diagram power supply LG 32 lh 35 fr

Contextual Info: ADVANCE M IC R O N MT58LC64K18B2 6 4 K x 18 SYNCHRONOUS SRAM I SYNCHRONOUS SRAM 64Kx 18 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns Fast OE: 5 ,6 and 7ns

93929

Contextual Info: MOTOROLA Order this document by MCM69T618/D SEMICONDUCTOR TECHNICAL DATA 64K x 18 Bit Synchronous Pipelined Cache Tag RAM MCM69T618 The MCM 69T618 is a 1 M-bit synchronous fast static RAM with integrated tag compare function. It is designed to address tag RAM for 512KB, 1MB, or 2MB

Contextual Info: HY6718100/101 HYUNDAI 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x 18 SR A M core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge

Contextual Info: M I CR ON T E C H N O L O G Y INC 3 SE » • bill 5 4*1 ODDEflfl? S ■ M R N ? = V á ~ 2 l-l¿ J 16K X 18 SRAM SRAM WITH ADDRESS / DATA INPUT LATCHES FEATURES • • • • • • Fast access times: 15,17,20 and 25ns Fast output enable: 6,8 and 10ns