CY82 Search Results

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

1MD45

Abstract: cy17 High-Zt11-12 CY10 CY82C691 CY82C692 CY82C693 DQ23P cy82
Contextual Info: PRELIM INARY CY82C692 W CYPRESS Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • Supports ail 3.3V Pentium™-class processors, AMD K5, K6 and Cyrix M1 CPUs • Two-bit wraparound counter supporting Intel Burst or Linear burst sequence

1de2

Abstract: northbridge circuit pentium 4 PS/2 KEYBOARD CONTROLLER 001H CY82C691 CY82C693UB intel 8042 keyboard controller 000B0000
Contextual Info: CY82C693UB P R E LIM IN A R Y hyperCache / Stand-Alone PCI Peripheral Controller with USB — CD ROM support Features PCI to ISA bridge PCI Bus Rev. 2.1 compliant Supports up to 5 additional PCI masters including the CY82C691 Integrated DMA controllers with Type A, B, and F sup­

SFF-8038i

Contextual Info: CY82C693 CYPRESS_ Pentium hyperCache™ Chipset Peripheral Controller — CD ROM support Features • PCI to ISA bridge • PCI Bus Rev. 2.1 compliant • Supports up to 5 additional PCI masters including the CY82C691 • Integrated DMA controllers with Type A, B, and F sup­

Contextual Info: CYPRESS PRELIMINARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Provides control for the cache, system memory, and the PCI bus PCI Bus Rev. 2.1 compliant Supports 3V Pentium™ , AMD K5, and Cyrix 6x86 M1 CPUs Support for WB or W T L1 cache

82c597

Abstract: 83C206 Cyrix 486 dx2 CX486 386DX CY82C597 intel 486 dx4 t324 amd 386 PC MOTHERBOARD diagram cyrix DX2
Contextual Info: PRELIMINARY CY82C597 386/486 Green Chip Set D Features Page mode DRAM controller supports mixture of 256KB/512KB/1MB/2MB/ 4MB/16MB devices D D MicrosoftR APM support 11 event detectors and 5 userĆdefined timers D D 160ĆPin single chip PQFP Supports PC/AT compatible systems

CY82C693

Contextual Info: PRELIMINARY CY82C693 Pentium hyperCache™ Chipset Peripheral Controller Features • PCI to ISA bridge • PCI Bus Rer. 2.1 compliant • Supports up to 5 additional PCI masters including die CY82C691 • Integrated DMA controllers with Type A, B, and F support.

Contextual Info: J5T ADVANCED INFORMATION CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states • Fully registered inputs and outputs in Pipelined mode operation • 16K x 64 common I/O architecture

Contextual Info: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path/Integrated Cache for h C -VX, h C -D X Solutions Features Two-bit wraparound counter supporting Intel Burst or Linear burst sequence Supports 3-1-1-1 Level 2 cache operation up to 66 MHz bus speed

692CU

Abstract: 82c pci isa
Contextual Info: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path Controller with Integrated Cache Features • O n -C h ip 8-D ee p F IF O s s u p p o rt P o st-W ritin g /P re-R e ad ing PCI data • S u p p o rts all 3.3 V P e n tiu m ™ -c la s s p ro ces so rs , A M D

CX486

Abstract: 83C206 82C596 386D taga7 cyrix DX2 Cyrix 486 dx2 OT502 BIOS source code 386 3118D
Contextual Info: p yp: v « *1 X X PRELIMINARY CY82C597 - 386/486 Green Chip Set Features • 60-Pin single chip PQFP • Supports PC/AT compatible systems at 25/33/40/50 • Supports AMD, Cyrix level 1 w rite-back CPU • W rite-Back/W rite-Through cache with 32KB/64KB/128KB/256KB/512KB/1 MB cache size

x86 processor architecture

Abstract: CY82C691 CY82C692 CY82C694 FFF80000H pci arbiter CY82C693U pci ide chips
Contextual Info: fax id: 3850 Using the CY82C693U hyperCacheTM PCI Peripheral Controller in Stand-Alone Operation Mode Introduction controller, system memory controller, CPU bus controller, cache tag, and CPU-to-PCI bridge. The CY82C692 Data Path/Integrated Cache performs data steering between CPU

A2241

Abstract: 82C691 CY2254ASC-2 CY27C010 CY82C691 CY82C692 CY82C693 CY82C694 8kx1 RAM ma897
Contextual Info: 1CY 82C6 91 PRELIMINARY CY82C691 Pentium hyperCache™ Chipset System Controller Features • Supports mixed standard page-mode and EDO DRAMs • Supports the VESA Unified Memory Architecture VUMA • Support for standard 72-bit-wide DRAM banks • Supports non-symmetrical DRAM banks

6X86

Abstract: CY27C010 CY82C691 CY82C692 CY82C693 CY82C694
Contextual Info: 1CY 82C6 94 PRELIMINARY CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states • Synchronous pipelined operations with registered inputs and outputs • 16K x 64 common I/O architecture

82C693

Abstract: CY82C691 CY82C692 CY82C693 cy82
Contextual Info: ADVANCED INFORMATION D Features D D D PCI Bus Rev. 2.1 compliant Supports up to 5 additional PCI masters including the CY82C691 D Integrated DMA controllers with Type A, B, and F support. D D D D D Integrated Interrupt controllers Integrated timer/counters

82C596

Abstract: 486dx isa bios ami bios 486dx 83c206 cyrix 486 FASTEST KEYBOARD BIOS cx486 82c599 486DX2 AM486
Contextual Info: PRELIMINARY CY82C599 Intelligent PCI Bus Controller Features D Provides an interface between the PCI Local Bus and the CPU bus D D PCI Bus Rev. 2.0 compliant D Supports IntelR 486DX, 486DX2, 486SX, 486SL, P24T, AMD AM486 and Cyrix Cx486S2 M6/M7 CPUs D D

TDA 11106

Abstract: ami bios 486dx vesa local bus ldev intel 486SL 82c596 am486 Block Diagram AMI bios power management E5EF 486 system bus 486dx isa bios
Contextual Info: PRELIMINARY C Y PR E SS Features • Provides an interface between the PCI Local Bus and the CPU bus • PCI Bus Rev. 2.0 compliant • Supports Intel 486DX, 486DX2, 486SX, 486SL, P24T, AMD AM486 and Cyrix Cx486S2 M6/M7 CPUs • Interfaces with Cypress CY82C596 or

CY82C694

Abstract: cy82
Contextual Info: PRELIM INARY CYPH CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states » Synchronous pipelined operations with registered in­ puts and outputs • 16K x 64 common I/O architecture

82c691

Abstract: m040 m043 M046 CY10 CY2254ASC-2 CY27C010 CY82C691 CY82C693 cy82
Contextual Info: p - : : : îW j r y n n I? Q c I 1 i l l l D D PRELIMINARY CY82C690 Pentium hyperCache™ Chipset Data-Path/lntegrated Cache for hC-ZX Solution Features • Supports all 3.3V Pentium™ -class processors, AMD K5, and Cyrix M1 CPUs • Directly interfaces with CY82C691 and CY82C693 to

Contextual Info: CY82C693 Pentium hyperCache™ Chipset Peripheral Controller — CD ROM support Featu res • PCI to ISA bridge • PCI Bus Rev. 2.1 compliant • Supports up to 5 additional PCI masters including the CY82C691 • Integrated DMA controllers with Type A, B, and F sup­

Contextual Info: CY82C694 Pentium hyperCache™ Chipset 128KB Expansion RAM Featu res • U s er s e lecta b le tw o -b it w rap -aro u n d b urst c o u n te rs u p ­ porting Intel™ interleaved and lin ear b u st se q u e n c es • In te rfac es d ire c tly to hyp erC ache™ C h ip s et at 66 M Hz

amd 386 PC MOTHERBOARD diagram

Abstract: 83C206 diagram cq 60 motherboard cq 60 motherboard Cyrix 486 dx2 CQ940 CY82C597 cx486 cypress 1994 sram zero intel 486 dx4
Contextual Info: 1CY 82C5 97 PRELIMINARY CY82C597 386/486 Green Chip Set Features • 60-Pin single chip PQFP • Supports PC/AT compatible systems at 25/33/40/50 MHz • Supports AMD, Cyrix level 1 write-back CPU • Write-Back/Write-Through cache with 32KB/64KB/128KB/256KB/512KB/1MB cache size

CY2254ASC-2

Abstract: CY27C010 CY82C691 CY82C692 CY82C693 CY82C694 cy82
Contextual Info: 1CY 82C6 93 PRELIMINARY CY82C693 Pentium hyperCache™ Chipset Peripheral Controller Features • PCI to ISA bridge • PCI Bus Rev. 2.1 compliant • Supports up to 5 additional PCI masters including the CY82C691 • Integrated DMA controllers with Type A, B, and F support

Contextual Info: iT /. ^ rT^n r n n rs s g g g p p r L > i l H h b PRELIMINARY h CY82C694 - Pentium hyperCache™ Chipset 128KB Expansion RAM Features • Interfaces directly to hyperCache™ Chipset at 66 MHz with 0 wait states • Synchronous pipelined operations with registered in­