DQ10C Search Results

Contextual Info: in tj. 28F400BX-T/B, 28F004BX-T/B 4 MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY • x8/x16 Input/Output Architecture — 28F400BX-T, 28F400BX-B — For High Performance and High Integration 16-bit and 32-bit CPUs ■ Very High-Performance Read

Contextual Info: IBM14N1372 IBM14N3272 IBM14N6472 High Perform ance SRAM Modules Features • 256K, 512K, and 1MB secondary cache module family using Synchronous and Asynchronous SRAMs. • Organized as a 32K, 64K, or 128K x 72 package on a 4.3” x 1.1”, 160-lead, Dual Read-out DIMM

128KX16

Abstract: DQ10C
Contextual Info: BENCHMARQ_ bq4024/bq4024Y 128Kx16 Nonvolatile SRAM Features General Description ► D ata retention in th e absence of power The CMOS bq4024 is a nonvolatile 2,097,152-bit sta tic RAM organized as 131,072 w ords by 16 bits. The in te g ral control circu itry an d lith ­

Contextual Info: JÊL S» 1993 ADVANCE M IC R O N I .w r ^ w . ^ MT58LC64K18B2 64K x 18 SYNCHRONOUS SRAM SYNCHRONOUS SRAM 64Kx 18 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns

M29F800A3BT12

Abstract: m29f800a3br 29F800A
Contextual Info: Order this document by M29F800A3/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA M29F800A3 M29F800A2 8M CMOS Flash Memory Organization: 524,288 words x 16 bits 1,048,576 words x 8 bits Power Supply Voltage: V q c = 3.3 V ± 0.3 V Access Time: M29F800A3—80 = 80 ns Max

Contextual Info: ADVANCE 64K x 18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, PIPELINED, BURST COUNTER AND SINGLE CYCLE DESELECT FEATURES PIN ASSIGNMENT Top View • Fast access tim e s : 4 .5 ,5 ,6 ,7 and 8ns • Fast OE access time: 5 and 6ns • • • • • • • • •

Contextual Info: H Y 6 7 V 1 8 1 1 0 /1 1 1 64K X 18 Bit SYNCHRONOUS CMOS SRAM -HYUNDAI PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a positiveedge triggered clock K .

Contextual Info: PRELIMINARY MT58LC64K18B2/M1 64K X 18 SYNCBU RST SRAM I^ICZROiSI 64K x 18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS, BURST COUNTER FEATURES • • • • • • • • PIN ASSIGNMENT Top View Fast access times: 9 ,1 0 ,1 1 ,1 2 and 14ns

J-L0011

Abstract: display counter block diagram 7 seg cc ELLS 110 T42LC wram
Contextual Info: ADVANCE M IC R O N ^ MT42LC256K32A1 256K x 32 WRAM SCmMXOKK WRAM FEATURES PIN ASSIGNMENT Top View • Dual-port organization: 256K x 32 D RA M port 128 x 16 SAM port • Extended Data-Out operation (tPC=20ns) - 200 megabyte per second data burst rate on D RAM

BQ4025

Abstract: bq4025Y
Contextual Info: bq4025/bq4025Y BENCHM ARQ 256Kx16 Nonvolatile SRAM Features General Description ► D ata retention in th e absence of power The CMOS bq4025 is a nonvolatile 4,194,304-bit static RAM organized as 262,144 w ords by 16 bits. The in teg ral control circuitry an d lith ­

Contextual Info: Jüt %'• ADVANCE MT58LC64K18M1 64K X 18 SYNCHRONOUS SRAM MICRON I SEMICONDUCTOR MC SYNCHRONOUS SRAM 64K x 18 SRAM +3.3V SUPPLY WITH CLOCKED, REGISTERED INPUTS AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns

X28C010

Abstract: XM28C4096-15 XM28C4096-20 XM28C4096-25 DQ12C DQ111
Contextual Info: A dvance Inform ation XM28C4096 4Megabit Module 256K x 16 Bit 5 Volt, Byte Alterable E2PROM FEATURES DESCRIPTION • High Density 4 Megabit 256K x 16 E2PROM Module • Low Power CMOS technology — A ctive-Less than 100mA — Standby-Less than 2mA • Access Tim e of 150ns

Contextual Info: "HYUNDAI HY67V18110/111 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad­ dress counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a posrtiveedge triggered clock K .

Contextual Info: HY UN DA I 64K X HY6718100/101 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x 18 SRAM core, address registers, data input registers, a 2-bit burst address counter and pipelined output. All synchronous inputs pass through registers controlled by a positive-edge

Contextual Info: ADVANCE M IC R O N 64K X MT58LC64K18M1 18 SYNCHRONOUS SRAM 64K x 18 SRAM +3.3V SUPPLY W ITH CLOCKED, REGISTERED INPUTS AND LINEAR BURST COUNTER FEATURES • • • • • • • • • • • • PIN ASSIGNMENT Top View Fast access times: 9 ,1 0 ,1 2 and 17ns

Contextual Info: S G S -T H O M S O N D M a iC T G S tM O ! M 2 8 F 1 0 2 1 Megabit 64K x 16, Chip Erase FLASH MEMORY • FAST ACCESS TIME: 90ns ■ LOW POWER CONSUMPTION - Standby Current: 1OOpA Max ■ 10,000 ERASE/PROGRAM CYCLES ■ 12V PROGRAMMING VOLTAGE ■ TYPICAL BYTE PROGRAMMING TIME 10[is

Contextual Info: JUL S 9 1983 ADVANCE llilll— p n M I MT58LC64K18A6 64Kx 18 SYNCHRONOUS SRAM SYNCHRONOUS 64K x 18 SRAM g n r tlV I + 3 -3V SUPPLY, FULLY REGISTERED I/O AND LINEAR BURST COUNTER QR AM FEATURES • • • • • • • • • • • • • Fast access times: 7,10,12 and 15ns

Contextual Info: MICRON SEMICONDUCTOR INC b3E D • blllSM S 000057=5 T4 4 « U R N ADVANCE MICRON ■ 64K KMICOMDUCTOR MC SYNCHRONOUS SRAM M T58LC 64K 18F5 X 18 SYNCHRONOUS SRAM 64Kx 18 SRAM +3.3V SUPPLY, FULLY REGISTERED INPUTS AND LATCHED OUTPUTS FEATURES • • • •

Contextual Info: SGS-THOMSON M27V402 R f f lD ^ [ llL liO T IjîO ll i LOW VOLTAGE _ 4 Megabit 256K x 16 UV EPROM and OTP EPROM PRELIMINARY DATA • LOW VOLTAGE READ OPERATION: 3V to 5.5V ■ FAST ACCESS TIME: 120ns ■ LOW POW ER ’’CMOS” CONSUMPTION:

Contextual Info: unir n «i nim ii i mui i iiiij.j.m u i.HHiHnj; MICRON TECHNOLOGY INC b lllS H T 3flE D QG0SÖ73 S • MRN ADVANCE T 'H L -2Z - H 16K x 16 SRAM SRAM WITH A D D R E SS / DATA INPUT LATCHES a FEATURES • • • • • • • • • PIN A SSIG N M EN T Top View)

Contextual Info: MICRON TECHNOLOGY INC 7 36E D • b l l l S M 11! 0 0 0 2 ^ 2 1 , pi h i i in11 jjgiy iip.j“1v .ut*. w j' i. w - mT Wjgri 1 HHRN ADVANCE 11 7 = V 6 > 2 3 -W 16K X 18 SRAM SYNCHRONOUS SRAM W ITH CLOCKED, REGISTERED INPUTS >V >.-. < FEATURES • • • •

DQ380

Abstract: U4 Package ADQ36
Contextual Info: STI644006UD2-1OVG 168-PIN DIMMS 4M X 64 Bits SDRAM Unbuffered DIM M FEATURES GENERAL DESCRIPTION • Maximum frequency=100MHz tcc=10ns • Burst Mode Operation • Auto and self refresh capability (4096 cycles/64ms refresh) • • LVTTL compatible inputs and outputs

Z3A11

Abstract: A10113 M28F410 M28F420 TSOP56
Contextual Info: M28F410 M28F420 SGS‘THOMSON G ì . H O » iL I § T [ M ! [ l( S Ì 4 Megabit (x8 or x16, Block Erase) FLASH MEMORY PRELIMINARY DATA DUAL x8 and x16 ORGANIZATION SMALL SIZE PLASTIC PACKAGES TSOP56 and S044 MEMORY ERASE in BLOCKS - One 16K Byte or 8K Word Boot Block (top or

Contextual Info: in y A28F400BR-T/B 4-MBIT 256K X 16, 512K X 8 SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY Automotive Intel SmartVoltage Technology — 5V or 12V Program/Erase — 5V Read Operation Very High Performance Read — 80 ns Max. Access Time, 40 ns Max. Output Enable T