DM74 SERIES Search Results

18 pin dual 7-SEGMENT LED DISPLAY

Abstract: dtl 9936 common anode 7 segment 7405 power regulator advantages of 7805 regulator operation of 7805 regulator 7805 connection with full wave rectifier DM9374 DM74 DM9374N
Contextual Info: Revised March 2000 DM9374 7-Segment Decoder/Driver/Latch with Constant Current Sink Outputs General Description The DM74 is a 7-segment decoder driver incorporating input latches and output circuits to directly drive common anode LED displays. Ordering Code:

74ls series logic family

Abstract: SN74HC logic family CMOS 4000 TTL 74ALS CMOS 4000 Series family cmos logic 4000 series 74LS TTL 245 74ls TTL family 74ls series family cross reference cmos 4000
Contextual Info: INTEGRAL KOREA Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4

cmos logic 4000 series

Abstract: TTL 74ALS 74 series TTL NOT gate MM74HC CMOS 4000 Series family 74ls series logic family CMOS 4000 SN74HC logic family 74ls TTL family 74ALS
Contextual Info: z Cross Reference Characteristics Technology IK Semi Hitachi IN74 TTL CMOS 4000 On Semi Toshiba TI Philips Fairchild SN74 SN74 SN74 74 DM74 IN74LS HD74LS SN74LS SN74LS SN74LS 74LS DM74LS IN74ALS HD74ALS SN74ALS SN74ALS SN74ALS 74ALS DM74ALS IW4 HD14 MC14 TC4

ALS74

Abstract: AN-476 DM74 AN476 pnp transistor 1000v SCHOTTKY DIODES CROSS REFERENCE
Contextual Info: Fairchild Semiconductor Application Note October 1986 Revised March 2003 Guide to ALS and AS Introduction Since the introduction of the first bipolar Transistor-Transistor Logic TTL family (DM74), system designers have wanted more speed, less power consumption, or a combination of the two attributes. These requirements have

DN74LS33

Contextual Info: LS T T L DN74LS Series DN74LS33 DN74LS33 DM74.LS33 Quad 2-input P ositive NOR B uffers with Open C ollector Outputs • Description P-1 D N 7 4 L S 3 3 con tain s fo u r 2-in put positive iso latio n N O R b u ffe r gates w ith open co lle cto r o u tp u ts.

Contextual Info: LS TTL DN74LS Series DN74LS42 DN74LS42 DM74- LS B C D to D ecim al D ecod ers • Description P -2 D N 7 4 L S 4 2 is a b in a ry -c o d e d decim al t o d ecim al d e co d e r. ■ Features • • D u rin g invalid in p u t, all in p u ts b e co m e H IG H

Contextual Info: LS73A National Semiconductor DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold

54LS109

Abstract: 54LS109DMQB 54LS109FMQB DM54LS109AJ DM54LS109AW DM74LS109AN J16A M16A LS109 DM74LS109
Contextual Info: LS109A National Semiconductor 54LS109/DM54LS109A/DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

DM54LS73A

Abstract: DM54LS73AJ DM54LS73AW DM74LS73AM DM74LS73AN J14A M14A N14A W14B
Contextual Info: LS73A National Semiconductor DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

dm74 Series

Abstract: 63821 54LS112 54LS112DMQB 54LS112FMQB DM54LS112AJ DM54LS112AW DM74 DM74LS112AN LS112AM
Contextual Info: LS112A National Semiconductor 54LS112/DM54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

Contextual Info: LS112A National Semiconductor 54LS112/DM54LS112A/DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

Contextual Info: Z9A National SLA Semiconductor 54LS109/DM54LS109A/DM74LSJI09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and

DM74LS73AN

Abstract: DM74LS73A DS006372 DM54LS73AJ DM54LS73AW DM74LS73AM J14A M14A N14A W14B
Contextual Info: DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on

Contextual Info: LS109A National Semiconductor 54LS109/DM54LS109A/DM74LSJ09A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-trig­ gered J-K flip-flops with complementary outputs. The J and

54LS112

Abstract: 54LS112DMQB 54LS112FMQB 54LS112LMQB DM54LS112AJ DM54LS112AW DM74LS112A DM74LS112AM DM74LS112AN DM74LS112
Contextual Info: DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the

6367-1

Contextual Info: LS107A National Semiconductor DM54LS107A/DM74LS107A Dual Negative-EdgeTriggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and

DM74LS74AN

Contextual Info: LS74A National ÉSA Semiconductor 54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

54LS74

Contextual Info: LS74A National Semiconductor 54LS74/DM54LS74A/DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the

DM74LS109AN

Abstract: DM54LS109AW DM74LS109A DM74LS109AM J16A 54LS109 54LS109DMQB 54LS109FMQB DM54LS109AJ
Contextual Info: DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the

DM74LS74AN

Abstract: DM74LS74A 54LS74 54LS74DMQB 54LS74FMQB 54LS74LMQB DM54LS74AJ DM54LS74AW DM74LS74AM DS006373
Contextual Info: DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

DM74LS107AN

Abstract: DM54LS107A DM54LS107AJ DM54LS107AW DM74LS107A DM74LS107AM J14A M14A N14A W14B
Contextual Info: DM54LS107A DM74LS107A Dual Negative-EdgeTriggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of

DM74LS76

Contextual Info: DM54LS76A/ DM74LS76A National MM Semiconductor DM54LS76A/DM74LS76A Dual Negative-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs General Description Absolute Maximum Ratings Note d This device con tains tw o independent negative-edgetriggered J-K flip -flo p s w ith com plem entary outputs.

Contextual Info: DM54LS73A/DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-trig­ gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of

74LS73AN

Abstract: Q356
Contextual Info: R C H U - P S E M IC O N D U C T O R tm DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs sition tim e of th e negative going edge o f the clock pulse. The data on the J and K inputs is allowed to change w hile the