DIODE MARK N10 Search Results

Contextual Info: H3E I SEUITRON INDUSTRIES LTD TJ • 813768=1 0000105 4 « S L C B 'T - W - T 'b TM SERIES- PI-RANGE Transient Voltage Suppressor ■Glass Passivated Junction Voltage Range 68V - 350 Volts ■100A Peak Pulse Current APPLICATIONS ■ Transient voltage suppression for induced lightning, NEMP,

esjc

Abstract: diode SM N6040 esjc03-09
Contextual Info: E S J C 0 3 9 kv S ± 'J M fl^tSSs : Outline Drawings HIGH VOLTAGE SILICON DIODE ESJC 03», ESJC03 is high reliability and high current capability type resin molded high voltage silicon diode which is sealed a multilayed mesa type silicon chip by epoxy resin.

Contextual Info: CM1410 4 Channel Headset EMI Filter with ESD Protection Features Product Description • The CM1410 is a quad low-pass filter array integrating four pi-style filters C-R-C that reduce EMI/RFI emissions while at the same time providing ESD protection. This device is custom-designed to interface with the

TRANSISTOR D2102

Abstract: L3003 TRANSISTOR ETP35KAN619U L3005 TRANSISTOR 1SR124-4AT82 transistor D454 D362 TRANSISTOR l3007 ma29ta5 TELEVISION EHT TRANSFORMERS
Contextual Info: TX-28/25/21MD4 Service Manual Safety Specifications Service Support Block Diagrams Parts List Service Information Adjustments Self Check Schematic Diagrams Service Hints Mechanical View Waveforms Supplementary Information This interface provides a link between the TV and

balun 75-ohm to 120-ohm

Abstract: I8051 capacitor 914 JJ201 E1-28 transformer intel 8051 timing characteristics e140 transformer 8051 timing diagram Balun cable 32 pair i8051 internal structure
Contextual Info: LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit Preliminary Datasheet The Intel LXT3108 is an octal 3.3V long haul short haul T1/E1/J1 Line Interface Unit LIU . This flexible LIU allows the design of T1/E1/J1 long haul and short haul multi-service cards

HI1-0509-5

Abstract: AN520 AN521 HI-506 HI-507 HI-508 HI-509 HI-549
Contextual Info: HI-506, HI-507, HI-508, HI-509 Data Sheet June 1999 File Number 3142.2 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers Features The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight

HI1-0509-5

Abstract: AN520 AN521 HI-506 HI-507 HI-508 HI-509 HI-549 Q11P HI9P0508-5
Contextual Info: HI-506, HI-507, HI-508, HI-509 TM Data Sheet October 2001 File Number 3142.4 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers Features The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight

HI1-0509-5

Abstract: AN520 AN521 HI-506 HI-507 HI-508 HI-509
Contextual Info: HI-506, HI-507, HI-508, HI-509 Data Sheet July 21, 2005 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for

Intel d101 motherboard diagram schematic

Abstract: MOTHERBOARD INTEL d101 intel D102 motherboard intel 9100 80549KC a006 ae02 marking core i3 mother board circuit marking h06 SMA marking code H16
Contextual Info: Dual-Core Intel Itanium® Processor 9000 and 9100 Series Dual-Core Intel® Itanium® Processor 1.6 GHz with 24 MB L3 Cache 9050 Dual-Core Intel® Itanium® Processor 1.6 GHz with 18 MB L3 Cache 9040 Dual-Core Intel® Itanium® Processor 1.6 GHz with 8 MB L3 Cache 9030

80960KA

Abstract: 80960KB 80960MC 270775
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

ta80960kb

Abstract: LADI 12V VAX-11
Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

a4490

Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Contextual Info: PRELIMINARY 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

TA80960KB

Abstract: 2T818 tl741
Contextual Info: intJ 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

Power Supply Supervisor iw 1688

Abstract: 754for
Contextual Info: intei 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Commercial • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ On-Chip Floating Point Unit

i960 Cx Instruction Set Quick Reference

Contextual Info: in t e i, 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

80960KA

Abstract: 80960KB 80960MC TA80960KA pga 132 packaging
Contextual Info: 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached Instructions

hi3-508-5

Abstract: HI9P508-5 HI3-507-5 hi3-509-5 HI9P506-9 HI1-508-2 HI1-509-5 hi1-506-5 HI9P508 HI9P508-9
Contextual Info: HI-506, HI-507, HI-508, HI-509 Data Sheet October 30, 2007 Single 16 and 8/Differential 8-Channel and 4-Channel CMOS Analog Multiplexers The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for

Contextual Info: Preliminary Datasheet Dual 1A, 1.5MHZ Synchronous Step-down DC-DC Converter AP3427M General Description Features The AP3427M is a high efficiency step-down dual channel DC-DC voltage converter. The chip operation is optimized by peak-current mode architecture with built-in synchronous power

Contextual Info: BQQ SSP-21116 ILC DATA DEVICE C O RPO RATIO N_ 270 VDC SOLID-STATE POWER CONTROLLERS FEATURES: DESCRIPTION The SSP-21116 Series of 270 Volt, dc, Solid-State Power Controllers SSPCs replace electromagnetic circuit breakers and solid-state relays rated from 5

Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors

Contextual Info: intei 80960KA EMBEDDED 32-BIT MICROPROCESSOR • High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped — Parallel Load/Decode for Uncached

Contextual Info: 80960KB EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING POINT UNIT High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS* Sustained Execution at 25 MHz Built-In Interrupt Controller — 31 Priority Levels, 256 Vectors

D15105

Abstract: 44fl5 271060 754for
Contextual Info: in te i 80960MC EMBEDDED 32-BIT MICROPROCESSOR WITH INTEGRATED FLOATING-POINT UNIT AND MEMORY MANAGEMENT UNIT Military High-Performance Embedded Architecture — 25 MIPS Burst Execution at 25 MHz — 9.4 MIPS1 Sustained Execution at 25 MHz On-Chip Memory Management Unit

Contextual Info: Ä G S M A N G E O M [F iG M T D @ të 80960XA EMBEDDED 32-BIT MICROPROCESSOR WITH 33RD TAG BIT TO SUPPORT OBJECT-ORIENTED PROGRAMMING AND DATA SECURITY Military • On-Chip Memory Management Unit — 4 Gigabyte Linear Address Space per Task — 4 Kbyte Pages with Supervisor/User