DINP Search Results

742 ggt

Abstract: D176G ZZ6.8
Contextual Info: 53,+3. .K[D176GB/ =?/8696.>?<2 69>2<8216.>2 ;:A2< <27.B 3GDQROGP Y 9B nrdo^cdib ^\k\]dgdot Gdg` Oj2>F57895; Y Dm``k\b`3^g`\m\i^` _dno\i^`A<hh Y 9fW _d`g`^omd^ nom`iboc .]`or``i ^jdg \i_ ^jio\^on/ Y 5 Gjmh B h``on WEF 4;440 4:75 m`diajm^` dinpg\odji Gdg` Oj2>8444:5<6

Contextual Info: DPR175A600VPR-170/290 PHASE MONITOR 17.5mm DIN Rail 17.5mm DINProtection Rail TimerRelay ATC-DIVERSIFIED ATCDIVERSIFIED.com 800-727-5646 Features: ! 3Ø - 3 Wire Input ! Monitors , Phase Sequence, Under Voltage, Over Voltage ! Trip delay T -0.2 to 10Sec

322125

Contextual Info: THIS DRAWING IS COPYRIGHT UNPUBLISHED. 19 RELEASED BY AMP FOR ALL I NC OR P O R A T E D . PUBLICATION RIGHTS , 19 LOC RESERVED. DI S T G REVISIONS 14 LTR REVISED F D DESCRIPTION PER 0L20-0178-97 D ATE DWN APVD 03N0V97 DKS CHK D DINPUES METALL I C IN5UUAT

Contextual Info: THI S DRAWING I S UNPUBLISHED. CO PYRIGHT RELEASED FOR PUBLICATION 19 BY AMP INCORPORATED. AL L R I G H T S , 19 DIST LOC RESERVED. G REVISIONS 14 LTR REVISED PER 0L20-0178-97 F D D ESCRIPTION DATE DWN APVD 300CT97 DKS CHK D DINPDE5 METALLIC 1 5DEE 5 . 0 0 ± 0 •08

Contextual Info: 64-,4 ?A097:7/@A>3 7:@3>9327/@3 <;C3> >38/E 4JGUVSJT Hdg` Oj5A G8:;<8> ^ 87C nrdo^cdib ^\k\]dgdot ^ 8 Hjmh C \i_ 8 Hjmh E ^jiadbpm\odjin B 2 3 ^ Tp]hdid\opm`3 no\i_\m_ QED g\tjpo ^ Qg\nod^ n`\g`_ \i_ agps kmjja`_ otk`n \q\dg\]g` Hdg` Oj5A ;778997; ^ VM dinpg\odji ntno`hA Eg\nn H

BJG 36

Contextual Info: 53,+3. =?/8696.>?<2 69>2<8216.>2 ;:A2< <27.C 3HESTQHR \ :C nrdo^cdib ^\k\]dgdot Hdg` Oj3?G689:6< \ Em``k\b`4^g`\m\i^` _dno\i^`B=hh \ :fW _d`g`^omd^ nom`iboc /]`or``i ^jdg \i_ ^jio\^on0 @ 1 2 \ 6 Hjmh C h``on WFG 5<551 5;86 m`diajm^` dinpg\odji \ 6 Hjmh E h``on WFG 5;86 m`diajm^` dinpg\odji

Contextual Info: 42*+*2 7585-=>;1 4534 :9@1; ;16-A 2EBOPMEN V ;5<fX _d`g`^omd^ nom`iboc Idg` Pj5A H8:;<8> /]`or``i ^jdg \i_ ^jio\^on0 V K`\qt gj\_ pk oj =9<7XD ? 0 1 V L_`\g ajm hjojm nrdo^cdib Idg` Pj5A ;77:8;87 V RFE g\tjpon \q\dg\]g` V WN dinpg\odji ntno`hA Fg\nn I V Hiqdmjih`io\g amd`i_gt kmj_p^o /TjKU ^jhkgd\io0

Contextual Info: THI S DRAWING I S UNPUBLISHED. CO PYRIGHT RELEASED FOR PUBLICATION 19 BY AMP INCORPORATED. AL L R I G H T S , 19 LOC RESERVED. DI ST G REVISIONS 14 LTR c D D ESCRIPTION REVISED PER 0L20-0178-97 DATE DWN APVD 300CT97 DKS CHK D DINPLE5 METALLIC 5LE 6 . 7 3 ± 0 •13

s4 2g

Abstract: SM-38 A56A GP 948 IR P 648 H gp 647 648 bgg
Contextual Info: 97;5 /KRD37<G0 2DC?=?C:E6 A6<2G 7LIVWTLU , Nd^mj hdid\opm` , Tdibg` m`g\t - _jp]g` m`g\t \q\dg\]g` Ejp]g` , Tdg`io _jp]g` m`g\t \q\dg\]g` Tdibg` , Djdg dinpg\odji ^g\nn I /7>6 CZSNJIO 2SSONJIVNRQU , SjIT - FMW ^jhkgd\io Ejjm gj^fdib ntno`hn2 Jhhj]dgdu`mn2 T`\o \_epnoh`io2

LHi 858

Contextual Info: 42*+*2 7585-=>;1 4534 :9@1; ;16-B 2FCPQNFO W ;5<fX _d`g`^omd^ nom`iboc Idg` Pj5A H8:;<8> /]`or``i ^jdg \i_ ^jio\^on0 W K`\qt gj\_ pk oj =9<7XD ? 0 1 W L_`\g ajm hjojm nrdo^cdib Idg` Pj5A ;77:8;87 W RFE g\tjpon \q\dg\]g` W WN dinpg\odji ntno`hA Fg\nn I W Hiqdmjih`io\g amd`i_gt kmj_p^o /TjKU ^jhkgd\io0

Contextual Info: SN74F378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE S D FS 030B - D2932, M ARCH 1987 - REVISED O CTO B ER 1993 Contains Six D-Type Flip-Flops With Single-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Buffered Common Enable Input

Contextual Info: SN54LVT273, SN74LVT273 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR I SCBS130E - MAY 1992 - REVISED JULY 1995 State-of-the-Art Advanced BICMOS Technology ABT Design for 3.3-V Operation and Low-Static Power Dissipation Support Mixed-Mode Signal Operation (5-V

Contextual Info: SN54LV174A, SN74LV174A HEX D-TYPE FLIP-FLOPS WITH CLEAR SCLS401C – APRIL 1998 – REVISED MAY 2000 D D D D D D D EPIC  Enhanced-Performance Implanted CMOS Process Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDAS207D - APRIL 1982 - REVISED MAY 1996 D D D D ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs ’ALS175 and ’AS175B Contain Four

A115-A

Abstract: LVTH273 SN54LVTH273 SN74LVTH273 SN74LVTH273DW SN74LVTH273DWR
Contextual Info: SN54LVTH273, SN74LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D SN54LVTH273 . . . J PACKAGE SN74LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

DDR2-667

Abstract: SSTUA32864 SSTUA32866 SSTUA32S865 TFBGA160
Contextual Info: SSTUA32S865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 16 March 2007 Product data sheet 1. General description The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory

SSTUA32864

Abstract: SSTUA32866
Contextual Info: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

DDR2-800

Abstract: SSTUA32864 SSTUA32866 E6G3
Contextual Info: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

74LV374

Abstract: 74HC374 74HCT374 74LV374D 74LV374N DIP20 JESD22-A114E SO20 SSOP20
Contextual Info: 74LV374 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 02 — 14 May 2009 Product data sheet 1. General description The 74LV374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input CP and an output enable

4032V

Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
Contextual Info: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj

74LVC16373A

Abstract: 74LVC16373ADGG 74LVC16373ADL 74LVCH16373A 74LVCH16373ADGG 74LVCH16373ADL TSSOP48
Contextual Info: INTEGRATED CIRCUITS DATA SHEET 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Product specification Supersedes data of 2002 Oct 02 2003 Dec 08 Philips Semiconductors Product specification 16-bit D-type transparent latch with 5 V

T574D

Abstract: 54HC 74HCT 564C 534LC
Contextual Info: ^ Supertex ine. HCT374 HCT534 HCT564 HCT574 Octal Edge-Triggered Flip Flops Ordering Information Package 20-pin plastic DIP 20-pin CERDIP 20-pin ceramic side-brazed DIP 20-pin ceramic leadless chip carrier Outputs Commercial 74HCT Non-Inverting 74H C T 374P

SC11017CN

Abstract: sim 300 modem at commands set SC11017 SC11017CV 74LS306 SC11014
Contextual Info: SC11017 Enhanced Parallel Bus Modem Controller SIERRA SEMICONDUCTOR □ □ Direct interface to SC11004, S C I 1014 and S C I 1015 single chip m odem s Built-in U A RT □ □ □ Com plete "A T " comm and set in firm w are Direct IBM PC bus interface 28-pin D IP or PLCC package

ALS174

Abstract: SN54ALS174 SN54ALS175 SN54AS174 SN54AS175B SN74ALS174 SN74ALS175 SN74AS174 SN74AS175B
Contextual Info: SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDAS207E - APRIL 1982 - REVISED MAY 2002 D D D ’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs ’ALS175 and ’AS175B Contain Four