LVTH273 Search Results

Contextual Info: Prelim inary A I P C H April 1999 I L D Revised April 1999 E M I C Q N D U C T G R tm LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Preliminary General Description The LVTH273 is a high-speed, low -pow er positive-edgetriggered octal D-type flip-flop featuring separate D-type

74LVTH273

Abstract: 74LVTH273MTC 74LVTH273SJ 74LVTH273WM LVTH273 M20D MS-013 MTC20
Contextual Info: p U ly19h " , , i1999 c o o Revised July E M IC O N D U C T G R T M LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features T he LVTH273 is a high-speed, low -pow er positive-' triggered octal D -type flip-flop featuring separate D-type

LVTH273

Abstract: 74LVTH273 74LVTH273MTC 74LVTH273SJ 74LVTH273WM M20D MS-013 MTC20
Contextual Info: Revised November 2000 LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear

LVTH273

Abstract: 74LVTH273 74LVTH273MTC 74LVTH273MTCX 74LVTH273SJ 74LVTH273WM M20D MS-013 MTC20 MAR64
Contextual Info: Revised March 2005 LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear

LVTH273

Abstract: 74LVTH273 74LVTH273MTC 74LVTH273SJ 74LVTH273WM M20D MS-013 MTC20
Contextual Info: Revised July 1999 LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear

Contextual Info: Revised July 1999 LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear

Contextual Info: Preliminary S E M [ C O N D U C T O R TM LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Preliminary General Description The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock (CP) and Clear

74LVTH273SJ

Abstract: 74LVTH273WM LVTH273 M20D MS-013 MTC20 74LVTH273 74LVTH273MTC
Contextual Info: LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Features General Description • Input and output interface capability to systems at The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear

Contextual Info: p ly19h " , ly ,i c o o Revised Ju 1999 E M IC O N D U C T G R T M LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low -pow er positive-edgetriggered octal D-type flip-flop featuring separate D-type

A115-A

Abstract: LVTH273 SN54LVTH273 SN74LVTH273 SN74LVTH273DW SN74LVTH273DWR
Contextual Info: LVTH273, LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D LVTH273 . . . J PACKAGE LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

Contextual Info: LVTH273, LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D LVTH273 . . . J PACKAGE LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

lxh273

Abstract: A115-A LVTH273 SN54LVTH273 SN74LVTH273 SN74LVTH273DW SN74LVTH273DWR
Contextual Info: LVTH273, LVTH273 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCBS136L – MAY 1992 – REVISED MARCH 2002 D D D D D D description These octal D-type flip-flops are designed specifically for low-voltage 3.3-V VCC operation, but with the capability to provide a TTL interface

lvth16244a

Abstract: LVT16244A LVT244A LVTH LVT241 LVT16245A LVT16244 LVT125 LVT16835 LVT240
Contextual Info: LVTĆtoĆLVTH Conversion Application Report 1999 Logic Products Printed in U.S.A. 0299 SCEA010 LVT-to-LVTH Conversion SCEA010 January 1999 1 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest

Contextual Info: LVTH273ĆEP 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOP WITH CLEAR SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 D Controlled Baseline D D D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: LVTH273, LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D LVTH273 . . . J PACKAGE LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

LVT244A

Abstract: LVT16244A LVTH16244A SCBD154 LVTH LVT162245 LVT125 LVT16835 LVT240 LVT241
Contextual Info: LVT-to-LVTH Conversion SCEA010 January 1999 1 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest

Contextual Info: LVTH273, LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D LVTH273 . . . J PACKAGE LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

SN74LVTH273PWR

Contextual Info: LVTH273, LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D LVTH273 . . . J PACKAGE LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

Contextual Info: LVTH273ĆEP 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOP WITH CLEAR SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 D Controlled Baseline D D D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

Contextual Info: LVTH273ĆEP 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOP WITH CLEAR SCBS769A − NOVEMBER 2003 − REVISED JUNE 2006 D Controlled Baseline D D D D D D D D D D Bus Hold on Data Inputs Eliminates the − One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing

LVTH273

Abstract: SN54LVTH273 SN74LVTH273
Contextual Info: LVTH273, LVTH273 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCBS136K – MAY 1992 – REVISED APRIL 1999 D D D D D D D D CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK LVTH273 . . . FK PACKAGE

lxh273

Abstract: A115-A LVTH273 SN54LVTH273 SN74LVTH273 SN74LVTH273DW SN74LVTH273DWR
Contextual Info: LVTH273, LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D LVTH273 . . . J PACKAGE LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

A115-A

Abstract: LVTH273 SN54LVTH273 SN74LVTH273 SN74LVTH273DW SN74LVTH273DWR
Contextual Info: LVTH273, LVTH273 3.3ĆV ABT OCTAL DĆTYPE FLIPĆFLOPS WITH CLEAR SCBS136M − MAY 1992 − REVISED OCTOBER 2003 D D D LVTH273 . . . J PACKAGE LVTH273 . . . DB, DW, NS, OR PW PACKAGE TOP VIEW 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10

3040-1-D

Contextual Info: LVTH273, LVTH273 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCBS136J - MAY 1992 - REVISED APRIL 1998 CLR [ 1 • • Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop • Typical V q l p Output Ground Bounce < 0.8 V at VCc = 3.3 V, TA = 25°C