DFN1410 Search Results

7B SMD

Contextual Info: Surface Mount SMD Packaging Reel and Carrier Tape Specifications MINIMUM PACKING QUANTITY DFN Series (Notes 4) DFN0806 DFN0808 Bulk Type Quantity NA NA NA DFN1006 NA DFN1010 NA DFN1409, DFN1410 DFN/QFN3030 (Note 5) DFN4030-12 DFN4030-12 Type B, C, D NA NA

Contextual Info: 74AUP1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed (Top View) for low power and extended battery life in portable applications. The 74AUP1G126 is a single non-inverting buffer/bus driver designed

74AUP1G86SE

Contextual Info: 74AUP1G86 SINGLE 2 INPUT EXCLUSIVE-OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G86 is a single 2-input positive exclusive-OR gate with a

74AUP1G07SE-7

Abstract: 74AUP1G07
Contextual Info: 74AUP1G07 SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G07 is a single buffer gate with an open drain output

NX3008NBKMB

Abstract: IP4303CX4 PCMF2DFN1
Contextual Info: Safeguard sensitive ICs - Increase battery life - Save space With NXP key products as recommended in this brochure Interface / Function Description Product type Package NFC antenna protection 18 / 24 V Birectional low capacitance ESD protection diode PESD18VF1BL

Contextual Info: High PSRR LDOs Dual Channel LDOs with High PSRR Performance Package DFN1612-8 SOT1225 LD6935 Series Size (mm) 1.6 x 1.2 x 0.4 mm Ptot @ °C (mW) VIN (V) 600 Quiescent Output PSRR @ current noise typ 1 kHz (µA) * (µVrms) (dB) 1.75 5.5 30 50 80 IOUT (mA)

SCHMITT-TRIGGER

Abstract: 74lvc1g17se-7 74LVC1G17
Contextual Info: 74LVC1G17 SINGLE SCHMITT-TRIGGER BUFFER Description Pin Assignments Top View The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with NC 1 a standard totem pole output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The

Contextual Info: 74LVC1G97 CONFIGURABLE MULTIPLE-FUNCTION GATE Description Pin Assignments Top View The 74LVC1G97 is a single 3-input positive configurable multiple function gate with a standard push-pull output. The output state is determined by eight patterns of 3-bit input.

Contextual Info: 74LVC1G02 SINGLE 2 INPUT POSITIVE NOR GATE Description Pin Assignments Top View ( Top View ) The 74LVC1G02 is a single 2-input positive NOR gate with a standard push-pull output. The device is designed for operation with A 1 5 Vcc A 1 5 Vcc B 2 a power supply range of 1.65V to 5.5V. The inputs are tolerant to

Contextual Info: 74AUP1G14 SINGLE SCHMITT-TRIGGER INVERETER Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is ( Top View ) designed for low power and extended battery life in portable ( Top View ) applications. NC 1 5 Vcc The AUP1G14 is a single 1-input Schmitt-trigger inverter gate with

Contextual Info: 74AUP1G17 SINGLE SCHMITT-TRIGGER BUFFER Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed ( Top View ) for low power and extended battery life in portable applications. ( Top View ) NC 1 The AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a

Contextual Info: 74AUP2G17 DUAL SCHMITT TRIGGER BUFFERS Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G17 is composed of two Schmitt trigger buffers with

Contextual Info: 74LVC1G08 SINGLE 2 INPUT POSITIVE AND GATE Description Pin Assignments The 74LVC1G08 is a single 2-input positive AND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing

Contextual Info: 74AUP1G09 SINGLE 2 INPUT POSITIVE AND GATE WITH OPEN DRAIN OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable ( Top View ) applications. ( Top View ) 5 Vcc

circuit diagram wireless spy camera

Abstract: PDTB123Y IP4303CX4 dual cc BAW62 3267 tsop6 PCMF2DFN1 BST60 PUMD4 PDTB123E PDTA143
Contextual Info: Discrete Semiconductors Selection Guide 2014 Protection and signal conditioning devices, diodes, bipolar transistors, MOSFETs and thyristors. NXP’s next generation of packaging DFN Discrete Flat No-lead packages – high performance on smallest footprint

Contextual Info: 74LVCE1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments Top View The 74LVCE1G126 is a single non-inverting buffer/bus driver with a 3-state output. The output enters a high impedance state when a LOW-level is applied to the output enable (OE)

AA112A

Abstract: IPC-7351A
Contextual Info: PACKAGE OUTLINE DIMENSIONS AP02002 SUGGESTED PAD LAYOUT(AP02001) (Based on IPC-7351A) Table of Contents X4-DFN0402‐2/SWP . 10

JESD30E

Abstract: 74AUP1G00
Contextual Info: 74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G00 is a single 2-input positive NAND gate with a

Marking code VM sot35

Abstract: VM MARKING CODE SOT353
Contextual Info: 74LVC1G07 SINGLE BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description Pin Assignments The 74LVC1G07 is a single inverter gate with an open drain Top View output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The input is tolerant to 5.5V

Contextual Info: 74LVC1G32 SINGLE 2 INPUT POSITIVE OR GATE Description Pin Assignments The 74LVC1G32 is a single 2-input positive OR gate with a Top View standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The A 1 5

Contextual Info: 74LVC1G98 CONFIGURABLE MULTIPLE-FUNCTION GATE Description Pin Assignments Top View The 74LVC1G98 is a single 3-input positive configurable multiple function gate with a standard push-pull output. The output state is determined by eight patterns of 3-bit input.

sot35

Contextual Info: 74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN DRAIN OUTPUT Description Pin Assignments Top View The 74LVC1G06 is a single inverter gate with an open drain output. The device is designed for operation with a power NC 1 supply range of 1.65V to 5.5V. The input is tolerant to 5.5V

74LVC1G02W57

Contextual Info: 74LVC1G02 SINGLE 2 INPUT POSITIVE NOR GATE Description Pin Assignments Top View (Top View) The 74LVC1G02 is a single 2-input positive NOR gate with a standard push-pull output. The device is designed for A 1 operation with a power supply range of 1.65V to 5.5V. The

Contextual Info: 74LVC1G97 CONFIGURABLE MULTIPLE-FUNCTION GATE Description Pin Assignments The 74LVC1G97 is a single 3-input positive configurable multiple function gate with a standard push-pull output. The output state is determined by eight patterns of 3-bit input. The user can chose the logic functions MUX, AND, OR,