DFN1409 Search Results

7B SMD

Contextual Info: Surface Mount SMD Packaging Reel and Carrier Tape Specifications MINIMUM PACKING QUANTITY DFN Series (Notes 4) DFN0806 DFN0808 Bulk Type Quantity NA NA NA DFN1006 NA DFN1010 NA DFN1409, DFN1410 DFN/QFN3030 (Note 5) DFN4030-12 DFN4030-12 Type B, C, D NA NA

Contextual Info: 74LVC1G02 SINGLE 2 INPUT POSITIVE NOR GATE Description Pin Assignments Top View ( Top View ) The 74LVC1G02 is a single 2-input positive NOR gate with a standard push-pull output. The device is designed for operation with A 1 5 Vcc A 1 5 Vcc B 2 a power supply range of 1.65V to 5.5V. The inputs are tolerant to

Contextual Info: 74AUP1G14 SINGLE SCHMITT-TRIGGER INVERETER Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is ( Top View ) designed for low power and extended battery life in portable ( Top View ) applications. NC 1 5 Vcc The AUP1G14 is a single 1-input Schmitt-trigger inverter gate with

Contextual Info: 74AUP1G17 SINGLE SCHMITT-TRIGGER BUFFER Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed ( Top View ) for low power and extended battery life in portable applications. ( Top View ) NC 1 The AUP1G17 is a single 1-input Schmitt-trigger buffer gate with a

Contextual Info: 74LVC1G08 SINGLE 2 INPUT POSITIVE AND GATE Description Pin Assignments The 74LVC1G08 is a single 2-input positive AND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing

Contextual Info: 74AUP1G09 SINGLE 2 INPUT POSITIVE AND GATE WITH OPEN DRAIN OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable ( Top View ) applications. ( Top View ) 5 Vcc

AA112A

Abstract: IPC-7351A
Contextual Info: PACKAGE OUTLINE DIMENSIONS AP02002 SUGGESTED PAD LAYOUT(AP02001) (Based on IPC-7351A) Table of Contents X4-DFN0402‐2/SWP . 10

Contextual Info: 74LVC2G34 DUAL BUFFERS Description Pin Assignments The 74LVC2G34 is a dual buffer gate with standard push-pull outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to

Contextual Info: 74LVC2G14 DUAL SCHMITT TRIGGER INVERTERS Description Pin Assignments The 74LVC2G14 is a dual Schmitt trigger inverter gate with standard push-pull outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing

Contextual Info: 74LVC1G00 SINGLE 2 INPUT POSITIVE NAND GATE Description Pin Assignments The 74LVC1G00 is a single 2-input positive NAND gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to

Contextual Info: 74LVC1G02 SINGLE 2 INPUT POSITIVE NOR GATE Description Pin Assignments Top View ( Top View ) The 74LVC1G02 is a single 2-input positive NOR gate with a standard push-pull output. The device is designed for operation with A 1 5 Vcc A 1 5 Vcc B 2 a power supply range of 1.65V to 5.5V. The inputs are tolerant to

Contextual Info: 74LVC1G17 SINGLE SCHMITT-TRIGGER BUFFER Description Pin Assignments The 74LVC1G17 is a single 1-input Schmitt-trigger buffer with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to

Contextual Info: 74LVC1G86 SINGLE 2 INPUT EXCLUSIVE OR GATE Description Pin Assignments The 74LVC1G86 is a single 2-input EXCLUSIVE OR gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to

Contextual Info: 74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments The 74LVC1G125 is a single non-inverting buffer/bus driver with a 3-state output. The output enters a high impedance state when a HIGH-level is applied to the output enable OE pin. The device is

Contextual Info: 74LVC2G07 DUAL BUFFERS with OPEN DRAIN OUTPUTS Description Pin Assignments The 74LVC2G07 is a dual buffer gate with open drain outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The input is tolerant to 5.5V allowing this device to be used

Contextual Info: 74AUP1G32 SINGLE 2 INPUT POSITIVE OR GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. ( Top View ) ( Top View ) The 74AUP1G32 is a single 2-input positive OR gate with a standard

74LVc1t45

Abstract: MARKING CODE FX4 MARKING CODE FX4 SOT363 74LVC1T45W6
Contextual Info: 74LVC1T45 SINGLE BIT DUAL POWER SUPPLY TRANSLATING TRANSCEIVER WITH 3 STATE OUTPUTS Description Pin Assignments The 74LVC1T45 is a single bit, dual supply transceiver with 3-state Top View outputs suitable for transmitting a single logic bit across different

74LVC1T45Z6

Contextual Info: 74LVC1T45 SINGLE BIT DUAL POWER SUPPLY TRANSLATING TRANSCEIVER WITH 3 STATE OUTPUTS Description Pin Assignments The 74LVC1T45 is a single bit, dual supply transceiver with 3-state outputs suitable for transmitting a single logic bit across different voltage domains. The A input/output pin is designed to track VCCA

Contextual Info: 74LVC1G86 SINGLE 2 INPUT EXCLUSIVE OR GATE Description Pin Assignments The 74LVC1G86 is a single 2-input EXCLUSIVE OR gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V

Contextual Info: 74AUP1G08 SINGLE 2 INPUT POSITIVE AND GATE Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed ( Top View ) for low power and extended battery life in portable applications. ( Top View ) 5 Vcc A 1 The 74AUP1G08 is a single 2-input positive AND gate with a

Contextual Info: 74AUP1G126 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description Pin Assignments The Advanced Ultra Low Power AUP CMOS logic family is designed for low power and extended battery life in portable applications. ( Top View ) ( Top View ) The 74AUP1G126 is a single non-inverting buffer/bus driver designed

Contextual Info: 74LVC1G34 SINGLE BUFFER GATE Description Pin Assignments The 74LVC1G34 is a single buffer gate with a standard push-pull output. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this

sot26 sot363 Z1

Contextual Info: 74LVC2G06 DUAL INVERTERS with OPEN DRAIN OUTPUTS Description Pin Assignments The 74LVC2G06 is a dual inverter gate with open drain outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The input is tolerant to 5.5V allowing this device to be used

Contextual Info: 74LVC2G17 DUAL SCHMITT TRIGGER BUFFERS Description Pin Assignments The 74LVC2G17 is a dual Schmitt trigger inverter gate with standard push-pull outputs. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing