DDR21 Search Results

NT5TU128M8DE

Abstract: NT5TU64M16DG nt5tu64m16dg-Bd NT5TU128M8DE-BD NT5TU256M4DE nt5tu64m NT5TU64M16 NT5TU64M16DG-3C NT5TU64M16DG-3CI NT5TU64M16DG-BE
Contextual Info: NT5TU256M4DE / NT5TU128M8DE / NT5TU64M16DG NT5TB256M4DE / NT5TB128M8DE / NT5TB64M16DG 1Gb DDR2 SDRAM Feature CAS Latency Frequency -37B/-37BI -3C/-3CI -AD/-ADI -AC/-ACI/-ACL -BE -BD DDR2-533 DDR2-667 DDR2-800 DDR2-800 DDR2-1066 DDR2-1066 4-4-4 5-5-5 6-6-6

SSTUA32864

Abstract: SSTUA32866
Contextual Info: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

NT5TU32M16CG-BD

Abstract: NT5TU32M16CG-be NT5TU64M8CE
Contextual Info: NT5TU128M4CE / NT5TU64M8CE /NT5TU32M16CG 512Mb DDR2 SDRAM C-Die Features • 1.8V ± 0.1V Power Supply Voltage • Data-Strobes: Bidirectional, Differential • Programmable CAS Latency: 3,4,5,6 and 7 • 4 internal memory banks • Programmable Additive Latency: 0, 1, 2, 3, and 4

IMX6DQ6SDLSRM

Contextual Info: Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX6DQIEC Rev. 2.3, 07/2013 MCIMX6QxCxxxxC MCIMX6DxCxxxxC i.MX 6Dual/6Quad Applications Processors for Industrial Products Package Information Case FCPBGA 21 x 21 mm, 0.8 mm pitch Ordering Information

Contextual Info: Spansion Analog and Microcontroller Products The following document contains information on Spansion analog and microcontroller products. Although the document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion

Contextual Info: Spansion Analog and Microcontroller Products The following document contains information on Spansion analog and microcontroller products. Although the document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion

IMX6DQ6SDLSRM

Contextual Info: Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX6DQAEC Rev. 2.3, 07/2013 MCIMX6QxAxxxxC MCIMX6DxAxxxxC i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors Package Information Case FCPBGA 21 x 21 mm, 0.8 mm pitch Ordering Information

W971GG6JB

Abstract: 8X12 DDR2-667 DDR2-800 0A80
Contextual Info: W971GG6JB 8M  8 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

sony cmos sensor imx 117

Abstract: sony IMX 117 imx 117 sensor sony cmos sensor imx 174 sony IMX 135 sony CMOS sensor imx 135 225/sony cmos sensor imx IMX 206 imx 117
Contextual Info: Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX6DQAEC Rev. 3, 03/2014 MCIMX6QxAxxxxC MCIMX6QxAxxxxD MCIMX6DxAxxxxC MCIMX6DxAxxxxD i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors Package Information Case FCPBGA 21 x 21 mm, 0.8 mm pitch

Contextual Info: Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX6DQIEC Rev. 2.1, 07/2013 MCIMX6QxCxxxxC MCIMX6DxCxxxxC i.MX 6Dual/6Quad Applications Processors for Industrial Products Package Information Case FCPBGA 21 x 21 mm, 0.8 mm pitch Ordering Information

sony cmos sensor imx 175

Abstract: sony IMX 132 CMOS Sony IMX 183 sony IMX 145 image sensor DDR21 imx cmos sony sony IMX 140 sensor sony cmos sensor imx 071
Contextual Info: Document Number: MCIMX35SR2CEC Rev. 8, 04/2010 MCIMX35 i.MX35 Applications Processors for Industrial and Consumer Products Package Information Plastic package Case 5284 17 x 17 mm, 0.8 mm Pitch Silicon Revisions 2.0 and 2.1 Ordering Information See Table 1 on page 3 for ordering information.

MT47H128M8CF-25

Abstract: 8 resistor array 10k smd 103
Contextual Info: 1Gb: x8, x16 Automotive DDR2 SDRAM Features Automotive DDR2 SDRAM MT47H128M8 – 16 Meg x 8 x 8 banks MT47H64M16 – 8 Meg x 16 x 8 banks Options1 Features • • • • • • • • • • • • • • • • • • • Marking • Configuration

samsung EMMC user guide

Abstract: Jedec lpddr2 samsung lpddr2 Mobile RAM samsung eMMC 4.5 MX53UG n78c AMBA AXI dma controller designer user guide lpddr2 layout SONY VTR M15 DIAGRAM DDR3 jedec
Contextual Info: Freescale Semiconductor Data Sheet: Advance Information Document Number: IMX53AEC Rev. 4, 11/2011 MCIMX53xA i.MX53xA Automotive and Infotainment Applications Processors Package Information Plastic Package Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch Ordering Information

sony cmos sensor imx 174

Abstract: Sony "IMX 175" CMOS
Contextual Info: Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX6DQAEC Rev. 2.1, 07/2013 MCIMX6QxAxxxxC MCIMX6DxAxxxxC i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors Package Information Case FCPBGA 21 x 21 mm, 0.8 mm pitch Ordering Information

pin vga CRT pinout

Abstract: samsung* lpddr2 LPDDR2-800 i.MX53 PCIMX535DVV1C emmc DDR pcb layout Samsung eMMC 4.41 LPDDR2 PoP JESD209-2 flexcan2
Contextual Info: Freescale Semiconductor Data Sheet: Advance Information Document Number: IMX53CEC Rev. 3, 7/2011 MCIMX53xD i.MX53xD Applications Processors for Consumer Products Package Information Plastic Package Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch Case FC-PBGA PoP 12 x 12 mm

HYB18T1G160C2F-25F

Abstract: HYB18T1G400C2F-3S HYB18T1G800C2F-25F HYI18T1G160C2F-3 DDR2-800E
Contextual Info: January 2008 HY[B/I]18T1G400C2[C/F] HY[B/I]18T1G800C2[C/F] HY[B/I]18T1G160C2[C/F] 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.02 Internet Data Sheet HY[B/I]18T1G[40/80/16]0C2[C/F] 1-Gbit Double-Data-Rate-Two SDRAM

Contextual Info: ESMT M14D5121632A 2H Operation Temperature Condition (TC) -40°C~95°C DDR II SDRAM 8M x 16 Bit x 4 Banks DDR II SDRAM Features z JEDEC Standard z VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V z VDD = 1.75V ~ 1.9V, VDDQ = 1.75V ~ 1.9V (for speed grade -1.8) z

M14D1G166

Abstract: m14d1g M14D1G1664A m14d1g16 DDRII esmt
Contextual Info: ESMT M14D1G1664A 2D 7DDR II SDRAM 8M x 16 Bit x 8 Banks DDR II SDRAM Features  JEDEC Standard  VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V  Internal pipelined double-data-rate architecture; two data access per clock cycle  Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

NT5CB64M16AP-CF

Abstract: nt5cb64m16 NT5CB64M16AP-CG NT5CB64M16AP nanya NT5CB64M16AP NT5CB64m NT5CB64M16AP-BE nt5cb64m16ap-dh MPR 20 20 CF RESISTOR NT5CB64M16AP-AC
Contextual Info: 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature  Write Leveling  1.5V ± 0.075V JEDEC Standard Power Supply  OCD Calibration  8 Internal memory banks (BA0- BA2)  Dynamic ODT (Rtt_Nom & Rtt_WR)  Differential clock input (CK, )

Contextual Info: W9712G6KB 2M  4 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

W971GG6KB

Abstract: W971GG6KB-3 W971GG6KB-25 W971GG6KB25
Contextual Info: W971GG6KB 8M  8 BANKS  16 BIT DDR2 SDRAM Table of Contents1. GENERAL DESCRIPTION . 4 2. FEATURES . 4

Contextual Info: Nanya Technology Corp. DDR3 L 4Gb SDRAM NT5CB(C)512M8CN / NT5CB(C)256M16CP NT5CB(C)512M8CN / NT5CB(C)256M16CP Commercial, Industrial and Automotive DDR3(L) 4Gb SDRAM Features  Signal Integrity  JEDEC DDR3 Compliant - Configurable DS for system compatibility

Contextual Info: 2Gb: x8, x16 Automotive DDR2 SDRAM Features Automotive DDR2 SDRAM MT47H256M8 – 32 Meg x 8 x 8 banks MT47H128M16 – 16 Meg x 16 x 8 banks Options1 Features • • • • • • • • • • • • • • • • • • • • Marking • Configuration

HYB18T1G400C2FL-3

Abstract: HYB18T1G400C2F-3S
Contextual Info: March 2008 HY[B/I]18T1G400C2[C/F] L HY[B/I]18T1G800C2[C/F](L) HY[B/I]18T1G160C2[C/F](L) 1-Gbit Double-Data-Rate-Two SDRAM DDR2 SDRAM Internet Data Sheet Rev. 1.20 Internet Data Sheet HY[B/I]18T1G[40/80/16]0C2[C/F](L) 1-Gbit Double-Data-Rate-Two SDRAM Revision History: Rev. 1.20, 2008-03