DDR1 SDRAM Search Results

ddr ram repair

Abstract: JESD79E JESD209 JESD209A DDR1 Ram Jedec JESD209 E2678A DDR 2 RAM REPAIR DSA91304A N5426A
Contextual Info: Agilent U7233A DDR1 Compliance Test Application with LPDDR and mobile-DDR Support for Infiniium Series Oscilloscopes Data Sheet Test, debug and characterize your DDR1 designs quickly and easily The Agilent Technologies U7233A DDR1 compliance test application

Contextual Info: Data Sheet Rev. 1.0 SDU12872H1BF2MT-50R 07-Apr-08 184-pin DDR1 PC3200 ECC DDR-SDRAM Module 01.2 5 13 4.7 DIMM 1GB DDR400 in TSOP Technique Features: • • • 184-pin 72-bit DDR1 Dual In-line Memory Module for desktop applications. DDR1-400 3.0-3-3 (CL-tRCD-tRP), 64Mx8 organized

ddr3 MTBF

Contextual Info: VCN60/70 Series www.murata-ps.com High Efficiency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION ESCRIPTIO ON NOT RECOMMENDED FOR NEW DESIGNS Designed signed to su support upport DDR1 DDR1, 1, DDR2 and DDR3 SDRA SDRAM

ddr3 MTBF

Abstract: SENSE23 4sp560m t
Contextual Info: VCN60/70 Series www.murata-ps.com High Efficiency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION ESCRIPTIO ON Designed signed to su support upport DDR1 DDR1, 1, DDR2 and DDR3 SDRA SDRAM AM memoryy power requ requirements,

modelsim 6.3f

Abstract: LFXP2-5E-5TN144C LFE3-17EA LFE3-17EA6FN484C LFE3-17E-6FN484CES sdram verilog lfxp25e5tn144c lfe3-17ea-6fn484c BT 1490 ddr2 pinouts
Contextual Info: DDR1 & DDR2 SDRAM Controller IP Cores User’s Guide August 2010 ipug35_04.7 Table of Contents Chapter 1. Introduction . 5 Quick Facts . 5

micron ddr3

Abstract: DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3 MT41J128M8 Verilog DDR memory model DDR3 "application note" DDR3 DQ flip flop IC
Contextual Info: Maxim > Design Support > App Notes > T/E Carrier and Packetized > APP 5120 Keywords: DDR1, DDR3, jitter, buffer, TDMoP, TDM over packet, DDR, SDRAM, PDV, PSN, double data rate APPLICATION NOTE 5120 Aug 26, 2011 Using a DDR3 Memory Module with the DS34S132

Contextual Info: Datasheet Regulator IC Series for Automotive Termination Regulator for DDR-SDRAMs BD35395FJ-M General Description Key Specifications         BD35395FJ-M is a termination regulator compatible with JEDEC DDR1/2/3/3L-SDRAM, which functions as a linear

Contextual Info: Datasheet 1.0V to 5.5V, 1A 1ch Termination Regulators for DDR-SDRAMs BD3539FVM BD3539NUX General Description Key Specifications          BD3539 is a termination regulator that complies with JEDEC requirements for DDR1-SDRAM, DDR2-SDRAM, and DDR3-SDRAM. This linear power

Contextual Info: VCN60/70 Series High Efficiency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION Designed to support DDR1, DDR2 and DDR3 SDRAM memory power requirements, the VCN60/70 Series point-of-load, non-isolated DC/DC converters have the high performance

Contextual Info: Datasheet 1.0V to 5.5V, 1A 1ch Termination Regulator for DDR-SDRAMs BD35390FJ Key Specifications General Description          BD35390FJ is a termination regulator that complies with JEDEC requirements for DDR1/2/3-SDRAM. This linear

mpc8543

Abstract: POWERPC E500 instruction set MPC8548 MPC8548E MPC8545
Contextual Info: Integrated Communications Processors MPC8548E PowerQUICC III Processor MPC8548/E PRODUCT SOLUTION Key Features The MPC8548E networking/telecom processor e500 core includes 512 KB L2 cache, an integrated XOR Acceleration security engine, 64-bit DDR1/2 scaling to 667

4SP560M T

Abstract: iso 9001 sanyo United Chemi-Con
Contextual Info: VCN60/70 Series High Efficiency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION Designed to support DDR1, DDR2 and DDR3 SDRAM memory power requirements, the VCN60/70 Series point-of-load, non-isolated DC/DC converters have the high performance

jedec MS-012-AA

Abstract: SP2996BEN CES7002A SP2996B
Contextual Info: Advanced SP2996B 2A Bus Termination Regulator VIN 1 FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5517 LINEAR INTEGRATED CIRCUIT 3A DDR BUS TERMINATION REGULATOR „ DESCRIPTION The UR5517 is a linear regulator which provides up to 3 Amp bi-directional sourcing and sinking capability for DDR1/2/3 SDRAM bus terminator applications. It only requires 20uF of ceramic output

UR5517

Abstract: MSOP-10 s3h-i
Contextual Info: UNISONIC TECHNOLOGIES CO., LTD UR5517 Preliminary LINEAR INTEGRATED CIRCUIT 3A DDR BUS TERMINATION REGULATOR „ DESCRIPTION The UR5517 is a linear regulator which provides up to 3 Amp bi-directional sourcing and sinking capability for DDR1/2/3 SDRAM bus terminator applications. It only requires 20uF of ceramic output

JESD8-15a

Abstract: ITT RZ2 SP2996 SP2996B CES7002A SP2996BEN TRANSISTOR HANDLING 2A
Contextual Info: SP2996B 2 Amp DDR Bus Termination Regulator FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection ■ Integrated Power MOSFETs

Contextual Info: Preliminary SP2996B 2A Bus Termination Regulator VIN 1 FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection

T37Z

Abstract: DD128 TSOP 66 pin Package thermal resistance DD128M82U3BB6 267-Mbps
Contextual Info: 1 GigaBit Stacked DDR1 SDRAM 128M x 8 DD55E, DD55ER Features • Low Profile 66 Ball Two-High Stacked Die micropede BGA • 77% Space Savings Over Two 66 Pin TSOP Packages • 50% Space Savings Over Two 60 Ball BGA Packages • Significant Space Savings and Reduced Parasitics and

Contextual Info: Data Sheet Rev.1.1 22.02.2010 512MB DDR1 – SDRAM SO-DIMM Features: Features: 1 200-pin 64-bit Small Outline, Dual-In-Line Double 200 PIN SO-DIMM SDN06464K1BE1HY-50R 1 512MB DDR PC3200 1 1 TSOP Technique RoHS compliant Options: 1 Frequency / Latency DDR 400 MHz CL3

SP2996B

Abstract: 470uF 25V TANT REGULATOR 2A SP2996BEN CES7002A
Contextual Info: SP2996B 2 Amp DDR Bus Termination Regulator FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection ■ Integrated Power MOSFETs

equivalent for transistor tt 2222

Abstract: BD3539 S 35390 bd35390fj MCR031002
Contextual Info: Hi-performance Regulator IC Series for PCs Termination Regulator for DDR-SDRAMs BD35390FJ No.09030EAT25 ●Description BD35390FJ is a termination regulator compatible with JEDEC DDR1/2/3-SDRAM, which functions as a linear power supply incorporating an N-channel MOSFET and provides a sink/source current capability up to 1A respectively. A built-in

DD256M

Abstract: T37Z TSOP 66 Package thermal resistance
Contextual Info: 1 GigaBit Stacked DDR1 SDRAM DD54E, DD54ER 256M x 4 Features • Low Profile 66 Ball Two-High Stacked Die micropede BGA • 77% Space Savings Over Two 66 Pin TSOP Packages • 50% Space Savings Over Two 60 Ball BGA Packages • Significant Space Savings and Reduced Parasitics and

Contextual Info: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot

Contextual Info: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot