DDR SGRAM Search Results
DDR SGRAM Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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TPS51200TDB1 |
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Sink/Source DDR Termination Regulator 0- |
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TPS51200TDB2 |
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Sink/Source DDR Termination Regulator 0- |
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LP2995LQ/NOPB |
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DDR Termination Regulator 16-WQFN 0 to 125 |
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TPS54672PWPR |
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6-A Active Bus Termination/ DDR Memory SWIFT Converter 28-HTSSOP -40 to 85 |
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LP2996LQ/NOPB |
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1.5A DDR termination regulator with shutdown pin for DDR2 16-WQFN 0 to 125 |
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DDR SGRAM Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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sdram pcb layout ddr
Abstract: MB81P643287 ram memory rambus 86-PIN FCRAM
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MB81P643287 256K-word 32-bit 86-pin MP-FS-20825-10/99 sdram pcb layout ddr MB81P643287 ram memory rambus FCRAM | |
SGRAM
Abstract: ddr SGRAM 1993 synchronous dram jedec dram ddr 1997
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125MHz SGRAM ddr SGRAM 1993 synchronous dram jedec dram ddr 1997 | |
ET 7273
Abstract: sdram schematic diagram 1993 SDRAM samsung mpp schematic DQS_ 1993 SDRAM
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125MHz MPP-JLEE-Q4-98 ET 7273 sdram schematic diagram 1993 SDRAM samsung mpp schematic DQS_ 1993 SDRAM | |
Contextual Info: 16M DDR SGRAM KM432D5131 16Mbit DDR SGRAM 128K x 32Bit x 4 Banks Double Data Rate Synchronous Graphic RAM with Bi-directional Data Strobe Revision 1.1 December 1998 Samsung Electronics reserves the right to change products or specification without notice. |
OCR Scan |
KM432D5131 16Mbit 32Bit 125MHz 143MHz/125 | |
KM432D5131TQ-G7
Abstract: KM432D5131TQ-G8 KM432D5131TQ-G0
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KM432D5131 16Mbit 32Bit 125MHz 143MHz/125MHz, 100MHz KM432D5131TQ-G7 KM432D5131TQ-G8 KM432D5131TQ-G0 | |
KM432D2131TQ-G0
Abstract: KM432D2131TQ-G6 KM432D2131TQ-G7 KM432D2131TQ-G8 1328G
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KM432D2131 64Mbit 32Bit KM432D2131TQ-G0 KM432D2131TQ-G6 KM432D2131TQ-G7 KM432D2131TQ-G8 1328G | |
3D Accelerator
Abstract: 128M-BIT 4mx32 INFINEON DETAIL 128-MBIT
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128-Mbit 32-Mbit 128Mbit 4Mx32, 300MHz, INFMP200104 3D Accelerator 128M-BIT 4mx32 INFINEON DETAIL | |
Contextual Info: ADVANCE 512K x 32 DDR SGRAM MICRON I TECHNOLOGY, INC. MT45V512K32 - 128K x 32 x 4 banks DOUBLE DATA RATE SGRAM For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/mti/msp/html/datasheet.html FEATURES • Internal, pipelined double data rate DDR architec |
OCR Scan |
MT45V512K32 | |
ddr sgram
Abstract: internal architecture of 555 SGRAM general architecture of ddr sdram TOP SIDE MARKING OF MICRON
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MT45V512K32 16MDDRSGBW ddr sgram internal architecture of 555 SGRAM general architecture of ddr sdram TOP SIDE MARKING OF MICRON | |
0909NS
Abstract: GDDR5 10x10mm, LGA, 44 pin 170-FBGA 60-LGA MARKING CL4 FBGA DDR3 x32 170FBGA 60-FBGA PC133 133Mhz cl3
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16K/16ms 4K/32ms 8K/64ms 16K/32ms 8K/32ms 2K/16ms 4K/64ms 429ns 667ns 0909NS GDDR5 10x10mm, LGA, 44 pin 170-FBGA 60-LGA MARKING CL4 FBGA DDR3 x32 170FBGA 60-FBGA PC133 133Mhz cl3 | |
4Mx32 BGA
Abstract: bga 8X16 4mx32 ddr 3 tsop 16M X 32 SDR SDRAM
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1Mx32 500MHz compel128M, 450MHz 300MHz 128MB) B166-H7962-X-X-7600 4Mx32 BGA bga 8X16 4mx32 ddr 3 tsop 16M X 32 SDR SDRAM | |
K5W1G
Abstract: KMCME0000M-B998 k9hbg08u1m K9MCG08U5M K5E1257ACM MC4GE04G5APP-0XA b998 KMCME0000M hd161hj K5D1G
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BR-07-ALL-001 K5W1G KMCME0000M-B998 k9hbg08u1m K9MCG08U5M K5E1257ACM MC4GE04G5APP-0XA b998 KMCME0000M hd161hj K5D1G | |
K8D3216UBC-pi07
Abstract: K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm
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BR-05-ALL-002 K8D3216UBC-pi07 K5E5658HCM KAD070J00M KBH10PD00M K5D1257ACM-D090000 samsung ddr2 ram MTBF KBB05A500A K801716UBC k5d1g13acm k5a3281ctm | |
micron ddr
Abstract: MT46V4M32
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128Mb: MT46V4M32 100-Pin 4M32DDR micron ddr | |
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Contextual Info: ADVANCE‡ 128Mb: x32 DDR SDRAM DOUBLE DATA RATE DDR SDRAM MT46V4M32 - 1 Meg x 32 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds FEATURES PIN ASSIGNMENT (TOP VIEW) 100-Pin TQFP (Normal Bend Shown) |
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128Mb: MT46V4M32 100-Pin 86IAMETER 4M32DDR | |
MT46V2M32Contextual Info: PRELIMINARY 64Mb: x32 DDR SDRAM DOUBLE DATA RATE DDR SDRAM MT46V2M32V1- 512K x 32 x 4 banks MT46V2M32 - 512K x 32 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds FEATURES PIN ASSIGNMENT (TOP VIEW) |
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MT46V2M32V1- MT46V2M32 100-Pin 2M32DDR-07 | |
MT46V2M32Contextual Info: 64Mb: x32 DDR SDRAM DOUBLE DATA RATE DDR SDRAM MT46V2M32V1- 512K x 32 x 4 banks MT46V2M32 - 512K x 32 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds FEATURES PIN ASSIGNMENT (TOP VIEW) 100-Pin TQFP |
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MT46V2M32V1- MT46V2M32 100-Pin 2M32DDR-07 | |
RISC-Processor s3c2410
Abstract: MR16R1624DF0-CM8 arm9 samsung s3c2440 architecture chip 3351 dvd sp0411n K9W8G08U1M sandisk micro SD Card 2GB arm9 s3c2440 K9F1G08U0A K6X8008C2B
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BR-04-ALL-005 BR-04-ALL-004 RISC-Processor s3c2410 MR16R1624DF0-CM8 arm9 samsung s3c2440 architecture chip 3351 dvd sp0411n K9W8G08U1M sandisk micro SD Card 2GB arm9 s3c2440 K9F1G08U0A K6X8008C2B | |
lg ddr sdram
Abstract: MT46V4M32
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128Mb: MT46V4M32 100-Pin 4M32DDR lg ddr sdram | |
1404UContextual Info: ADVANCE‡ 128Mb: x32 DDR SDRAM DOUBLE DATA RATE DDR SDRAM MT46V4M32 - 1 Meg x 32 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds FEATURES PIN ASSIGNMENT (TOP VIEW) 100-Pin TQFP DQ3 VDDQ DQ4 DQ5 VSSQ |
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128Mb: 096-cycle 4M32DDR 1404U | |
MT46V2M32Contextual Info: 64Mb: x32 DDR SDRAM DOUBLE DATA RATE DDR SDRAM MT46V2M32V1- 512K x 32 x 4 banks MT46V2M32 - 512K x 32 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds FEATURES PIN ASSIGNMENT (TOP VIEW) 100-Pin TQFP |
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MT46V2M32V1- MT46V2M32 100-Pin 2M32DDR-07 | |
a7a10Contextual Info: 64Mb: x32 DDR SDRAM DOUBLE DATA RATE DDR SDRAM MT46V2M32V1- 512K x 32 x 4 banks MT46V2M32 - 512K x 32 x 4 banks For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds FEATURES PIN ASSIGNMENT (TOP VIEW) 100-Pin TQFP |
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096-cycle 2M32DDR-07 a7a10 | |
JEDEC SPD No.21
Abstract: JEP106 001N
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13M32734BCD-260Y 31334D33323733344243442D323630592020 JEDEC SPD No.21 JEP106 001N | |
100-K12*10Contextual Info: www.fairchildsemi.com FAN6555 2A DDR Bus Termination Regulator Description • • • • • • • • • • The FAN6555 switching regulator is designed to convert voltage supplies ranging from 2.3V to 4V into a desired output voltage or termination voltage for DDR SDRAM memory. The FAN6555 can be implemented to produce regulated |
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FAN6555 FAN6555 DS30006554 100-K12*10 |