D47D Search Results

ACT8841

Abstract: sn74act8841 SN74AS8840 S/ACT8841
Contextual Info: SN 74A C T8841 Digital Crossbar Switch The S N 7 4 A C T 8 8 4 1 is a single-chip digital crossbar sw itch that cost-effectively eliminates bottlenecks to speed data through com plex bus architectures. The 'A C T 8 8 4 1 has 16 four-bit bidirectional ports w hich can be connected in

KTY87-205

Abstract: philips kty87 KTY87 R40 AH D 2578 HO-22 Silicon temperature sensors
Contextual Info: KTY87-205 PHILIPS INTERNATIONAL SbE D • ?110fl2b □D47D7I1 3T4 ■ PHIN SILICON TEMPERATURE SENSORS The K T Y 8 7 are high precision te m p e ra tu re sensors w ith a positive te m p e ra tu re c o e ffic ie n t o f resistance fo r tem perature measuring and te m perature c o n tro l. In th e te m perature range 10 ° C to 110 ° C th e

flip-flop 948

Abstract: 5252 f 1101 SN74AS8840 CNTR11-CNTR8 Zeus Component AS8832
Contextual Info: SN74AS8840. Digital Crossbar Switch • High-speed programmable switch for parallel processing applications • Dynam ically reconfigurable for fault-tolerant routing • 64 bidirectional data I/O s in 16 nibble four-bit groups • D ata I/O selection programmable by nibble

EDI8L24129V

Contextual Info: EDI8L24129V 128Kx24 SRAM 3.3 Volt FEATURES The EDI8L24129VxxBC is a 3.3V, three megabit SRAM constructed with three 128Kx8 die mounted on a multi-layer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V operating voltage, the EDI8L24129V is ideal for creating a single chip memory solution

Contextual Info: w t GEC P LESS EY S I M I C O N I I I O K S P1480 LAN CAM 1KX64-BIT CMOS CONTENT-ADDRESSABLE MEMORY (SUPERSEDES SEPTEMBER 1993 EDITIO N The P1480 LAN CAM is a 1K X 64-bit fixed-width CMOS Content-addressable Memory (CAM) aimed at address filtering applications in Local-area Network (LAN) bridges

7486 XOR GATE

Abstract: circuit diagram of half adder using IC 7486 7486 2-input xor gate ic 7486 XOR GATE pin configuration IC 7486 pin configuration of 7486 IC vhdl code for vending machine pin DIAGRAM OF IC 7486 data sheet IC 7408 laf 0001
Contextual Info: Lattice Semiconductor Handbook 1994 Click on one of the following choices: • Table of Contents • How to Use This Handbook • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. Lattice Semiconductor Handbook 1994 i Copyright © 1994 Lattice Semiconductor Corporation.

8l32128c

Abstract: block diagram of of TMS320C4X EDI8L32512C20AI EDI8L32512C TMS320C30 TMS320C32 DSP96002 EDI8L24128C EDI8L32256C
Contextual Info: EDI8L32512C 512K x 32 CMOS High Speed Static RAM FEATURES DESCRIPTION DSP Memory Solution • Motorola DSP96002 • Analog SHARC DSP • Texas Instruments TMS320C3x, TMS320C4x Random Access Memory Array • Fast Access Times: 12*, 15, 17, and 20ns • TTL Compatible Inputs and Outputs

AMD-K5-PR133ABR

Abstract: AMD-K5 PR100 Block Diagram AMD-K5-PR120ABR AMD-K5-PR133ABQ AMD-K5-PR166ABX AMD-K5-PR90ABQ P54C PR133 AMD-K5 tr-5-t
Contextual Info: AM D3 PRELIMINARY INFORMATION AMD-K5 Processor Data Sheet 18522F/0—Jam 997 1 AMD-K5 Processor Features • Four-issue su p erscalar core w ith six p a ra lle l execution un its arran g ed in a five-stage pipeline ■ 16-Kbyte, dual-tagged, four-way, set-associative instru ctio n

ADE-602-156

Abstract: RF 433 RR3 hitachi l200 2h2a0 ATI 216 bga ero IEC 384 14/2 fire alarm using IC 555 doc ic laf 0001 laf 0001 power MAS 10 RCD
Contextual Info: SuperH SH 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Hardware Manual HITACHI ÄDE-602-124A Rev. 2.0 03/02/99 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

HJ945020

Abstract: M21 M23 d43 309
Contextual Info: HJ945020 User’s Manual Ver.0.8 2001/05/18 HJ945020 User’s Manual Preliminary Ver.0.8 2001.05.18 1/17 HJ945020 User’s Manual Ver.0.8 2001/05/18 Contents 1. Overview 1.1. HJ945020 Outline 1.2. Usage Notes 1.3. Block Diagram 1.4. HJ945020 Features 1.5. External Memory Space

64K X 4 CACHE SRAM

Abstract: CARD-EDGE
Contextual Info: ISSI ISSI IS6MC512L IS6MC512L 512KB CMOS 3.1 COASt CACHE MODULE PRELIMINARY FOR THE INTEL PENTIUM CPU MARCH 1997 DESCRIPTION ISSI's IS6MC512L is an L2 cache module de- FEATURES • Low-cost, card-edge low-profile CELP module with 160 leads • For Intel Pentium CPU-based systems

d13d1

Abstract: 16P2N M62320P
Contextual Info: MITSUBISHI < STD. LINEAR ICs > M62320P,FP 2 8-BIT I/O EXPANDER for I C BUS GENERAL DESCRIPTION The M62320P/FP is a CMOS 8-bit I/O expander which has serial to parallel and parallel to serial data converting functions. It can communicate with a microcontroller via few wiring

IEC60956-3

Abstract: IEC60956-1 m8051 warp Biphase
Contextual Info: TAS3218 www.ti.com . SLES235 – JULY 2008 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE

wt 633-12

Abstract: PC motherboard intel i7 schematic diagram 2013 intel pentium 80501 5081M host pc recover target dead motherboard bios 20-pin debug header 2032M A20-A3 TR12 pentium processor block diagram ATIC 112
Contextual Info: D Pentium Processor Family Developer’s Manual Volume 1: Pentium® Processors NOTE: The Pentium® Processor Family Developer’s Manual consists of three books: Pentium® Processors, Order Number 241428; the 82496/82497/82498 Cache Controller and 82491/82492/82493 Cache

Contextual Info: PARADIGM PDM4M6224 PDM4M6225 COASt Compliant 256KB and 512KB Second Level Cache Modules with 5V 11-bit Tag Field for Intel Pentium CPUs Features Description □ Available in 256KB an d 512KB pipelined burst configurations. T he PD M 4M 6224 a n d PD M 4M 6225 are h ig h perform ance CMOS static RAM m odules. They are

a 4514 v

Abstract: BQ 6100 MARK 314 SN74AS8840 Zeus Component D43-D40
Contextual Info: SN74AS8840 Digital Crossbar Switch • H igh-speed program m able sw itch for parallel processing applications • D ynam ically reconfigurable for fault-tolerant routing • 64 bidirectional d ata I/O s in 16 nibble four-bit groups • D ata I /O selection program m able by nibble

pentium processor block diagram

Abstract: BT 815 transistor 82430fx pentium system software writers manual 241430 4558n 241429 TR12 Pentium A80501-60 2202m
Contextual Info: D Pentium Processor Family Developer’s Manual Volume 1: Pentium® Processors NOTE: The Pentium® Processor Family Developer’s Manual consists of three books: Pentium® Processors, Order Number 241428; the 82496/82497/82498 Cache Controller and 82491/82492/82493 Cache

Contextual Info: EDI8L32512C 512Kx32 CMOS High Speed Static RAM FEATURES DESCRIPTION  DSP Memory Solution The EDI8L32512C is a high speed, 5V, 16Mb SRAM. The device is available with access times of 12, 15, 17 and 20ns allowing the creation of a no wait state DSP memory solution. The high speed, 5v supply

0309H

Contextual Info: Q u a l it y S e m ic o n d u c t o r , I n c High-Speed CMOS 1 k x 64, 2k x 64 Content-Addressable Memory QCAM Associative Processor . QS761480 QS762470 FEATURES DESCRIPTION • • • • The QS761480 and QS762470 is a family of 1k and 2k x 64-bit CAMs (content-addressable memories).

Contextual Info: TAS3218 www.ti.com . SLES235 – JULY 2008 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE

PLCC weight

Abstract: DSP96002 EDI8L32512C DQ06 4 DQ04
Contextual Info: EDI8L32512C T NO 512K x 32 CMOS High Speed Static RAM DESCRIPTION n DSP Memory Solution • Motorola DSP96002 • Analog SHARC DSP • Texas Instruments TMS320C3x, TMS320C4x n Random Access Memory Array • Fast Access Times: 12*, 15, 17, and 20ns • TTL Compatible Inputs and Outputs

Contextual Info: TAS3218 www.ti.com . SLES235 – JULY 2008 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE

m8051 warp

Abstract: reverb effect IEC60958-1 d2s 28 diode interface zigbee with 8051 M8051 TAS3218 TAS3218IPZP TAS3218IPZPR TAS3218PZPR
Contextual Info: TAS3218 www.ti.com . SLES235 – JULY 2008 DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE

HJ945010

Abstract: hitachi l23
Contextual Info: HJ945010 User’s Manual Ver.0.8 2001/05/18 HJ945010 User’s Manual Preliminary Ver.0.8 2001.05.18 1/17 HJ945010 User’s Manual Ver.0.8 2001/05/18 Contents 1. Overview 1.1. HJ945010 Outline 1.2. Usage Notes 1.3. Block Diagram 1.4. HJ945010 Features 1.5. External Memory Space