D0073 Search Results

Biphase decoder

Abstract: BUS-1555 manchester Manchester block diagram BUS-63105 BUS-8559
Contextual Info: I L C DATA DEVICE CORP 32E ]> • Mt?07bR D0073b3 3 « D D C - f ~75^<77 C O R P O R A T IO N BUS-1555 MIL-STD-1553 MANCHESTER II DECODER FOR TEST EQUIPMENT FEA TU R ES • 16 MHz C LO C K R A T E DESCRIPTION AND APPLICATIONS Providing enhanced bit error capability

Contextual Info: Sk “TOSHIB A -CDISCKLTL/OH IÖ F 9097250 T O S H IB A D IS C R E T E /O P T O 2SA1328 TO TT SS D D00731b 56C 073L6 D 7 " - 3 _ SILICON PNP EPITAXIA L TYPE (PCT PROCESS) Unit in mm HIGH CURRENT SWITCHING APPLICATIONS. 1 Q 3 M A X . 0 3 .6 ± 0.2 FEATURES:

Contextual Info: TOSHIBA {DISCRETE/OPTO} 9097250 TOSHIBA ~SÌ DIS C R E T E/ OP TO 5 6C Ò F f ^ O T T E S O D0073ñE h |~~ 0 7 382 ù'7^-33~/<7 S IL IC O N PNP T R IP L E D IF F U SE D TYPE AUDIO FREQUENCY POWER AMPLIFIER APPLICATIONS. Unit in nun :0.3 MAX. F E A T U R E S :

BBC OS 0,9 4A

Abstract: 07380 bbc os 0.9 4A
Contextual Info: lb T O S H I B A -CDISC R E T E / O P T O } 909725 0 TO SHI BA T D i 7E S O Q Ü Q 1371 fc, | bbC <DISCRETE/OPTO 0 7 379 2SB993 SILICON PNP TRIPLE DIFFUSED TYPE PCT PROCESS) INDUSTRIAL APPLICATIONS Unit in mm HIGH CURRENT SWITCHING APPLICATIONS. POWER AMPLIFIER APPLICATIONS.

WJ-L1

Contextual Info: WJ-L1/SML1 5 TO 3000 MHz TO-8 THIN-FILM LIMITER MODULE ♦ AVAILABLE IN SURFACE MOUNT ♦ VOLTAGE VARIABLE LIMITING LEVEL: -10 TO O dBm ♦ LOW INSERTION LOSS AT LOW INPUT LEVELS: < 2.0 dB TYP. ♦ GOOD SUPPRESSION OF EVEN ORDER HARMONICS DUE TO BALANCED CIRCUIT DESIGN

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

sony SBX1610-52

Abstract: CXK* Sony CXK784861Q-33 sis 486 eads pinout sony motherboard diagram 5412J L29B 2SC895+SONY
Contextual Info: SONY CXK784861Q-33 DESCRIPTION FEATURES • Single Chip Cache Subsystem for 486 CPU • Look-aside Architecture • Write-back and Write-through Cache Opera­ tions • 33 Mhz Operating Frequency • 128K byte two-way-set associativity • Supports MESI protocol

7HC125

Abstract: ge 732t processor 8212 DDD7331 HP5082-2835 MP7641 MP7641AN MP7641AS MP7651
Contextual Info: MP7641 € • E X 4 8-C hannel Voltage Output 10 M H z Input Bandwidth 8-Bit Multiplying D AC s with Serial Digital Port R FEATURES • 8 Independent 2-Quadrant Multiplying 8-Bit DACs • Dual Positive +10 V and +5 V Supplies or Dual (±5 V) Supplies Capability

Contextual Info: b 2 4 c1 3 7 Q • • • • • • • • • • • • Transformerless 2-4 wire conversion Constant current with constant voltage fallback fo r long loops Loop start and ground start compatible TIP/RING polarity reversals TIP, RING high impedance enable/disable

Contextual Info: ~ INT ER NA TION AL RECTI FIE R 73 » | 4Û55452 00 07330 & | I O R INfTERNATioNAL r e c t i f i e r Data Sheet No. PD-2.169 R77R SERIES 600-400 VOLTS RANGE 7100 AMP AVG HOCKEY PUK DIFFUSED JUNCTION RECTIFIER DIODES VOLTAGE RATINGS PART HUHBER V rs H - IV

Contextual Info: SONY I CXK7791OATM/AYM » 2 131,072-word by 9-bit High Speed Synchronous Static RAM Description The CXK7791OATM/AYM is a high speed CMOS synchronous static RAM with common I/O pins, organized as 131,072-word by 9-bit. This synchronous SRAM integrates input registers, high

Contextual Info: @ LG Semicon. Co. LTD. Description Features The GMM7408110BS/SG is an 8M x 40 bits D y n a m ic R A M M O D U L E w h ic h is assembled 20 pieces o f 4M x 4 bit EDO DRAMs in 24 26 pin SOJ package on both side the printed circuit board with decoupling capacitors. The G M M 7408110BS/SG is

Contextual Info: MP7626 Microprocessor Com patible Buffered Multiplying 16-Bit Digital-to-Analog Converter FEATURES APPLICATIONS • • • • • • • • • • • • • Four Quadrant Multiplication 16-Bit Monotonicity Low Power Consumption TTL/5 V CMOS Compatible

Contextual Info: b3E D BROOKTREE CORP • IbMSSTS 0007311 flMb ■ BRK Interface Specification IS-510.12 Primary Rate CEPT Framer P a r t # U G A -5 1 0 March, 1993 B rod d rœ Brooktree Corporation 9950 Barnes Canyon Road San Diego, CA 92121 USA 619-452-7580 619-452-1249 fax

Contextual Info: HXILINX XC95108 In-System Programmable CPLD June 1,1 9 9 6 Version 1.0 Preliminary Product Specification Features Power Management • • 7.5 ns pin-to-pin logic delays on all pins foNT to 125 MHz • • • 108 macrocells with 2400 usable gates Up to 108 user I/O pins

Contextual Info: BAW56 SILICON PLANAR EPITAXIAL HIGH-SPEED DIODES Silicon planar high-speed switching series diode pair PACKAGE OUTLINE DETAILS ALL DIM ENSIONS IN m m M arking BAW56 = A l 3.0 2.8 0.14 0.09 0.48 0.38 J. 0.70 0.50 3 "11.4 Pin configuration 1 = CATHODE 2 = CATHODE

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid

pmi opo 7

Abstract: pmi op 02 z
Contextual Info: I ANALOG DEVICES/ PHI DIV □5 D OfllLAOS DODb^a T OP-08/883 PRECISION LOW-INPUT-CURRENT PMl OPERATIONAL AMPLIFIER P recisio n M o n o lith ics Inc. ~7< ?-'C > C r ~ /o 1.0 SCO PE This specification covers the detail requirements for a low-power operational amplifier.

TEA2024

Abstract: av2d
Contextual Info: S G S-THOMSON 7fiC D I 7 ^ 2 3 7 “ 0007320 T | 78C 07328 ~o" TEA2024 T ~ > H ~ o £ - o \ • m m sii ADVANCE INFORMATION STER EO A F A M P L IF IE R S TE R EO A F A M P L IF IE R The TEA2024 is an A .F , stereo am plifier in plastic package o f 10 passages

Contextual Info: @ LG Semicon. Co. LTD. Description Features The GMM7408200B S/SG is an 8M x 40 bits D y n a m ic R A M M O D U L E w h ic h is assembled 20 pieces of 4M x 4 bit DRAMs in 24 26 pin SOJ package on both side the p rin te d c irc u it board w ith d e co u p lin g

LM759

Abstract: qml-38535
Contextual Info: REVISIONS LTR DESCRIPTION DATE APPROVED YR-MO-DA REV SHEET REV SHEET REV STATUS OF SHEETS REV 1 SHEET PREPARED BY RICK C. OFFICER PMIC N/A STANDARDIZED MILITARY DRAWING 3 A 5 6 APPROVED BY MICHAEL A. FRYE 8 9 10 11 DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444

Contextual Info: L S I TECHNOLOGY VLSI I NC 47E ¡VTI » T e c h n o l o g y , in c . T - lS - H S - O H GOVERNMENT PRODUCTS DIVISION PREVIEW VM1553 BUS CONTROLLER REMOTE TERMINAL INTERFACE FEATURES • C om prehensive MIL-STD-1553B dual-redundant Bus C ontroller BC , Bus M onitor (BM), and Remote

Contextual Info: AT6000 Series Features • • • • • • • High Performance System Speeds to 70 MHz Flip-Flop Toggle Rates to 250 MHz Symmetrical Architecture Thousands of Registers Flexible Busing Network Predictable Timing Delays 100% Factory-Tested Cache Logic Design

3014 LED smd

Abstract: 5962-E368 qml-38535 28C512 28C513 BAS 3020 SLFCM 1S555
Contextual Info: 5962-E368 D IS T R IB U T IO N S T A T E M E N T A . A p p r o v e d fo r p u b lic r e l e j s e : d i m i b u l l o n is u n lim it e d . ^004706 0007360 ^Sfl 1. SCOPE 1.1 Scope. This drawing forms a part of a one part - one part nunber documentâtion system see 6.6