CY2D Search Results

Contextual Info: CY2DP814 1:4 Clock Fanout Buffer Features Description • Low-voltage operation The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. ■ VDD = 3.3V ■ 1:4 fanout ■

CY2DL814

Abstract: CY2DL814SC CY2DL814SCT CY2DL814SI CY2DL814SIT CY2DL814ZC CY2DL814ZCT CY2DL814ZI CY2DL814ZIT
Contextual Info: ComLink Series CY2DL814 1:4 Clock Fanout Buffer Features • • • • • • • • Low-voltage operation VDD = 3.3V 1:4 Fanout Single-input configurable for — LVDS, LVPECL, or LVTTL The Cypress CY2 series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the

Contextual Info: CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to 10 LVPECL output pairs ■ Translates any single-ended input signal to 3.3 V LVPECL

Contextual Info: CY2DL15110 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two low-voltage differential signal LVDS input pairs to distribute to 10 LVDS output pairs

Contextual Info: ComLink Series CY2DP3110 PRELIMINARY 1 of 2:10 Differential Fanout Buffer Features Description • Ten ECL/PECL differential outputs • Two ECL/PECL and HSTL differential or LVCMOS/LVTTL single-ended inputs • Hot-swappable/-insertable • 35-ps output-to-output skew typical

Contextual Info: FastEdge Series CY2DP3110 1 of 2:10 Differential Fanout Buffer Features Description • Ten ECL/PECL differential outputs • Two ECL/PECL and HSTL differential or single-ended inputs • Hot-swappable/-insertable • 35-ps output-to-output skew typical

Contextual Info: CY2DM1502 1:2 CML / LVPECL Input to CML Output Fanout Buffer Features Functional Description • One current mode logic CML or low-voltage positive emitter-coupled logic (LVPECL) input pair distributed to two CML output pairs ■ 20-ps maximum output-to-output skew

Input voltage 40V Output voltage 13.8V

Abstract: JEDEC SPEC MS - 034 JESD78B
Contextual Info: CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two low-voltage positive emitter-coupled logic LVPECL input pairs to distribute to 10 LVPECL output pairs ■ 40-ps maximum output-to-output skew

Contextual Info: ComLink Series CY2DL814 1:4 Clock Fanout Buffer 1:4 Clock Fanout Buffer Functional Description Features The Cypress CY2 series of network circuits is produced using advanced 0.35 micron CMOS technology, achieving the industry’s fastest logic. • Low-voltage operation

Contextual Info: CY2DP818 1:8 Clock Fanout Buffer 1:8 Clock Fanout Buffer Description Features The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. • Low-voltage operation VDD = 3.3 V ■ 1:8 fanout

Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, HCSL, or CML input pairs to distribute to four LVDS output pairs ■ 30-ps maximum output-to-output skew

CY2DP814

Abstract: CY2DP814SC CY2DP814SCT CY2DP814SI CY2DP814SIT CY2DP814ZC CY2DP814ZCT CY2DP814ZI CY2DP814ZIT
Contextual Info: ComLink Series CY2DP814 1:4 Clock Fanout Buffer Features Description • • • • • • • • • Low voltage operation VDD = 3.3V 1:4 fanout Single-input configurable for LVDS, LVPECL, or LVTTL Four differential pairs of LVPECL outputs Drives 50-ohm load

Q10A

Abstract: DD 127 D DL8520 CY2DL8520 Q11A Q13A 39 pin lvds converter q19b Q16b Q16A
Contextual Info: ADVANCED CY2DL8520 20 Bit Buffer/ Converter w/ Output Enable s ComL TM SERIES Product Features Product Features ( Cont.) • VDD range from 2.5 to 3.3V • • 20 input’s configurable for LVPECL/ LVTTL/LVCMOS 20 pairs LVDS output Drives 50/100 ohm load

CY2DP818

Contextual Info: ADVANCED CY2DP818 1:8 Clock Fanout Buffer TM ComL SERIES Product Features Product Description • This CYPRESS series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic. • • • • • 1:8 Fanout

Contextual Info: FastEdge Series CY2DP314 PRELIMINARY 1 of 2:4 Differential Fanout Buffer Features Description The CY2DP314 is a low-skew, low propagation delay 2-to-4 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The

Contextual Info: CY2DP814 1:4 Clock Fanout Buffer Features Description • Low-voltage operation The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. ■ VDD = 3.3V ■ 1:4 fanout ■

CY2DP314

Abstract: CY2DP314OI CY2DP314OIT CY2DP314OXI CY2DP314OXIT P314
Contextual Info: CY2DP314 1:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable

Contextual Info: FastEdge Series CY2DP3110 1 of 2:10 Differential Fanout Buffer Features Description • Ten ECL/PECL differential outputs • Two ECL/PECL and HSTL differential or single-ended inputs • Hot-swappable/-insertable • 35-ps output-to-output skew typical

CY2DP3110

Abstract: CY2DP3110AI CY2DP3110AIT CY2DP3110AXIT MC100ES6111
Contextual Info: FastEdge Series CY2DP3110 1 of 2:10 Differential Clock/Data Fanout Buffer Features Functional Description • Ten ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB)

2DL15

Abstract: 2DL-15 2VBQ
Contextual Info: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description • Select one of two differential LVPECL, LVDS, or CML input pairs to distribute to four LVDS output pairs ■ 30-ps maximum output-to-output skew

Contextual Info: CY2DP818 1:8 Clock Fanout Buffer 1:8 Clock Fanout Buffer Features Description • Low-voltage operation VDD = 3.3 V The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. ■ 1:8 fanout

CY2DP3110

Abstract: CY2DP3110AI CY2DP3110AIT MC100ES6111
Contextual Info: FastEdge Series CY2DP3110 1 of 2:10 Differential Clock/Data Fanout Buffer Features Functional Description • Ten ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB)

CY2DP3120

Abstract: CY2DP3120AI CY2DP3120AIT CY2DP3120AXI CY2DP3120AXIT MC100ES6221
Contextual Info: FastEdge Series CY2DP3120 1:20 Differential Clock/Data Fanout Buffer Features Functional Description The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The

p314v

Contextual Info: FastEdge Series CY2DP314 1 of 2:4 Differential Clock/Data Fanout Buffer Features Functional Description • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs CLKA • One HSTL differential or single-ended inputs (CLKB)