Q16A Search Results

MC14517

Abstract: 14517B Q32B Q32A
Contextual Info: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64−bit static shift register consists of two identical, independent, 64−bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data

jfet j102

Abstract: SLUA372 tda 0470 bq78PL118EVM SLUA524 SLUU481 smd zener diode code z4 USB-TO-GPIO cell balance board users guide Advanced Gas Gauge Host Firmware Guide
Contextual Info: User's Guide SLUU474 – January 2011 bq78PL116EVM Evaluation Module The bq78PL116EVM Evaluation Module can assist users in evaluating the bq78PL116 PowerLAN Master Gateway Controller. Included in this document are discussions of the board and its operation, the

SFH-1212A

Abstract: SFH-1212 diode c72 SFH 30A smd schottky diode s4 SOD-123 pwm e-bike laptop LCD SCHEMATIC
Contextual Info: bq78PL116 SLUSAB8B – OCTOBER 2010 – REVISED FEBRUARY 2011 www.ti.com PowerLAN Master Gateway Battery Management Controller With PowerPump™ Cell Balancing Technology Check for Samples: bq78PL116 FEATURES 1 • 23 • • • • • • • • •

DDR2-667

Abstract: SSTUA32864 SSTUA32866 SSTUA32S865 TFBGA160
Contextual Info: SSTUA32S865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications Rev. 02 — 16 March 2007 Product data sheet 1. General description The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory

SSTUA32864

Abstract: SSTUA32866
Contextual Info: SSTUG32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01 — 23 April 2007 Product data sheet 1. General description The SSTUG32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

DDR2-800

Abstract: SSTUA32864 SSTUA32866 E6G3
Contextual Info: SSTUM32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 2 March 2007 Product data sheet 1. General description The SSTUM32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

Contextual Info: 74SSTUB32868A www.ti.com SCAS846B – JULY 2007 – REVISED NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 DIMM PCB Layout • 1-to-2 Outputs Support Stacked DDR2 DIMMs

Contextual Info: 74SSTUB32868 www.ti.com . SCAS835C – JUNE 2007 – REVISED MARCH 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

J2 Q24A B

Abstract: ICS98ULPA877A ICSSSTUAF32868A IDTCSPUA877A Q17A-Q20A
Contextual Info: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description ICSSSTUAF32868A QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity

HD74SSTV32852

Abstract: HD74SSTV32852LBEL Q13A
Contextual Info: To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

7103

Abstract: ICS98ULPA877A IDT74SSTUBH32865A IDTCSPUA877A Q19A
Contextual Info: DATASHEET IDT74SSTUBH32865A 28-BIT 1:2 REGISTERED BUFFER FOR DDR2 Description The IDT74SSTUBH32865A includes a parity checking function. The IDT74SSTUBH32865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and

Contextual Info: C O S/M O S INTEGRATED CIRCUIT , hcc/ hcf «17B DUAL 64-STAGE STATIC SH IFT REGISTER • • • • • • • • • CLO C K FR EQ UENC Y 12 MHz TYP. A T V DD= 10V S C H M IT T T R IG G E R CLOCK INPUTS A L L O W O PE R ATIO N W ITH V E R Y SLOW CLO CK RISE

SN74SSTV32852-EP

Contextual Info: SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS w w w .t i.c om SCES700 – OCTOBER 2007 FEATURES 1 • Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Extended Temperature Performance of –40°C

ICS98ULPA877A

Abstract: IDT74SSTUBF32868A IDTCSPUA877A Q22B
Contextual Info: DATASHEET 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description occurred on the open-drain QERR pin active low . The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity,

Contextual Info: 74SSTUB32868A www.ti.com. SCAS846C – JULY 2007 – REVISED MARCH 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

74SSTUB32865

Abstract: 74SSTUB32865ZJBR Q19A
Contextual Info: 74SSTUB32865 www.ti.com SLAS537 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2

14517B

Abstract: MC14517B MC14517BCP MC14517BDW MC14517BDWR2
Contextual Info: MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data

SLG8SP553V

Abstract: KB926 LA4101P SP8K10 LM 4863 D FBMA-L11-201209-221LMA30T 4101p ich9 JMB385 compal notebook schematics
Contextual Info: A B C D E 1 1 Compal confidential 2 2 Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM+ICH9-M core logic 3 3 2008-01-01 4 4 Compal Secret Data Security Classification 2007/08/28 Issued Date 2006/03/10 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

74SSTUB32868A

Abstract: 74SSTUB32868AZRHR Q13A D1-D28
Contextual Info: 74SSTUB32868A www.ti.com. SCAS846C – JULY 2007 – REVISED MARCH 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SFH-1212

Abstract: smd schottky diode s4 SOD-123 pwm e-bike P13S
Contextual Info: bq78PL116 www.ti.com SLUSAB8A – OCTOBER 2010 – REVISED OCTOBER 2010 PowerLAN Master Gateway Battery Management Controller With PowerPump™ Cell Balancing Technology Check for Samples: bq78PL116 FEATURES 1 • 23 • • • • • • • • •

Contextual Info: 74SSTUB32868A www.ti.com. SCAS846C – JULY 2007 – REVISED MARCH 2009 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

Contextual Info: ICSSSTV32852 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registersProduct

Contextual Info: SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 04 — 22 April 2010 Product data sheet 1. General description The SSTUB32868 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank

Contextual Info: SSTUM32865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications Rev. 01 — 19 September 2007 Product data sheet 1. General description The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four 2R x 4 and similar high-density Double Data Rate 2 (DDR2) memory modules. It