CQ 765 Search Results

Contextual Info: Ol & National Semiconductor 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description Asynchronous Inputs: LOW input to Sq sets Q to HIGH level LOW input to C0 sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on Cq and S q makes both Q

df2e

Abstract: HH2C DE65 CQ 765
Contextual Info: 86.-6 @B2;9<91AB?5 >=D5? ?5:1E 6JGTURJS R R R R R R R R R t:=6 {@`l sceefjc C 4 5 t:=6 {@`l fbbdbbfe t:=6 {@`l q~qbkbbdbegbid 3=9: 3=<A13A 41A1 q@?E24E 2CC2?86>6?E co^ cq cbb> >2I` \2E co h.rq] q@?E24E C6D:DE2?46 ho dgb.oqaeb.rq z2I` DH:E49:?8 G@=E286 fbb.oq a cdg.rq

6C46

Abstract: E24ED BC 459 91AB A13A 2e65 4e24 bd 872
Contextual Info: 86.-6 @B2;9<91AB?5 >=D5? ?5:1E 6JGTURJS R R R R R R R R R t:=6 {@`lsceefjc t:=6 {@`lfbbdbbfe 3=<A13A 41A1 3=9: q@?E24E 2CC2?86>6?E co^ cq cbb> \2E co h.rq] u@=5 A=2E65l eb> \2E co h.rq] q@?E24E C6D:DE2?46 q@?E24E >2E6C:2= ho dgb.oqaeb.rq z2I` DH:E49:?8 G@=E286

df2e

Abstract: H R C M F 2J E-49 CP 2AA E236 dk qs
Contextual Info: 75-.-55 :8;80@A>4 7867 =<C4> >490D 5IFSTQIR R R R R R R R t:=6 {@`lsceefjc t:=6 {@`lq~qbkbbdbefegc 2<89 2<;@02@ 30@0 q@?E24E 2CC2?86>6?E co^ cp^ cq o8+?|d^ o8q5| q@?E24E >2E6C:2= q@?E24E C2E:?8 \*6D`=@25] z2I` DH:E49:?8 A@H6C +E2?52C5 v:89 q2A24:EJ jo dgb.oq aeb.rq

GK transistor

Abstract: I F462 91AB Z649 A13A BHEC DF2E
Contextual Info: 86.-6 @B2;9<91AB?5 >=D5? ?5:1E 6JGTURJS R R R R R R R R R t:=6 {@`l sceefjc C 4 5 t:=6 {@`l fbbdbbfe t:=6 {@`l q~qbkbbdbegbid 3=9: 3=<A13A 41A1 q@?E24E 2CC2?86>6?E co^ cq cbb> \2E co h.rq] u@=5 A=2E65l eb> \2E co h.rq] q@?E24E C6D:DE2?46 q@?E24E >2E6C:2= ho dgb.oqaeb.rq

91AB

Abstract: A13A DF2E 662D
Contextual Info: 86.-6 @B2;9<91AB?5 >=D5? ?5:1E 6JGTURJS R R R R R R R R R t:=6 {@`l sceefjc C 4 5 t:=6 {@`l fbbdbbfe t:=6 {@`l q~qbkbbdbegbid 3=9: 3=<A13A 41A1 q@?E24E 2CC2?86>6?E co^ cq cbb> \2E co h.rq] u@=5 A=2E65l eb> \2E co h.rq] q@?E24E C6D:DE2?46 q@?E24E >2E6C:2= ho dgb.oqaeb.rq

CY7C1317CV18

Abstract: CY7C1319CV18 CY7C1321CV18 CY7C1917CV18 512Kx9
Contextual Info: CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency

CY7C1310CV18

Abstract: CY7C1312CV18 CY7C1314CV18 CY7C1910CV18
Contextual Info: CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■

CY7C1311CV18

Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■

CY7C1311CV18

Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■

CY7C1317CV18

Abstract: CY7C1319CV18 CY7C1321CV18 CY7C1917CV18
Contextual Info: CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 ■ 300 MHz clock for high bandwidth ■ 4-word burst for reducing address bus frequency

CY7C1911BV18

Abstract: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1313
Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth

Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

CY7C1311BV18

Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth

GS8662T18BD

Contextual Info: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

GS81302T18GE-333

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS8662T08/09/18/36BD-400/350/333/300/250 72Mb SigmaDDR-IITM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS8662TT20/38BD-550/500/450/400/350 GS8662TT06/11BD-500/450/400/350 72Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features 550 MHz–350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O SRAMs. The GS8662TT06/11/20/38BD SigmaDDR-II+ SRAMs are just one element in a family of low power, low

Contextual Info: GS8662T20/38BD-550/500/450/400/350 GS8662T06/11BD-500/450/400/350 72Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features 550 MHz–350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O SRAMs are just one element in a family of low power, low

Contextual Info: GS8662TT20/38BD-550/500/450/400/350 GS8662TT06/11BD-500/450/400/350 72Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features 550 MHz–350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O SRAMs are just one element in a family of low power, low