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    CY7C1313 Search Results

    CY7C1313 Datasheets (55)

    Cypress Semiconductor
    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    CY7C131-30JC
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-30JC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-30JC
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-30JI
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-30JI
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-30JI
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-30LC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-30NC
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-30NC
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-35FMB
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35JC
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-35JC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35JC
    Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF 920.78KB 12
    CY7C131-35JC
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-35JI
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-35JI
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35JI
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-35LC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35LC
    Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF 920.78KB 12
    CY7C131-35LMB
    Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF 920.78KB 12
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    CY7C1313 Price and Stock

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    Infineon Technologies AG CY7C1313KV18-250BZXI

    IC: SRAM memory; 18MbSRAM; 1Mx18bit; FBGA165; parallel; -40÷85°C
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    TME CY7C1313KV18-250BZXI 136
    • 1 -
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    • 100 -
    • 1000 $31.34
    • 10000 $31.34
    Get Quote
    Avnet Americas CY7C1313KV18-250BZXI Tray 272
    • 1 -
    • 10 -
    • 100 -
    • 1000 $17.89
    • 10000 $16.21
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    Rochester Electronics CY7C1313KV18-250BZXI 1,585 1
    • 1 -
    • 10 -
    • 100 $21.05
    • 1000 $18.84
    • 10000 $17.73
    Buy Now
    Flip Electronics CY7C1313KV18-250BZXI 49
    • 1 $12.97
    • 10 $12.97
    • 100 $12.97
    • 1000 $12.97
    • 10000 $12.97
    Get Quote

    Infineon Technologies AG CY7C1313KV18-250BZC

    SRAM Chip Sync Dual 1.8V 18M-bit 1M x 18 0.45ns 165-Pin FBGA Tray
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical () CY7C1313KV18-250BZC 1,360 1,360
    • 1 -
    • 10 -
    • 100 -
    • 1000 -
    • 10000 $22.35
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    CY7C1313KV18-250BZC 82 1
    • 1 $17.92
    • 10 $17.92
    • 100 $17.92
    • 1000 $17.92
    • 10000 $17.92
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    Avnet Americas CY7C1313KV18-250BZC Tray 680
    • 1 -
    • 10 -
    • 100 -
    • 1000 $8.99
    • 10000 $8.12
    Get Quote
    Arrow Electronics CY7C1313KV18-250BZC 82 1
    • 1 $17.92
    • 10 $17.92
    • 100 $17.92
    • 1000 $17.92
    • 10000 $17.92
    Buy Now
    Flip Electronics CY7C1313KV18-250BZC 1,777
    • 1 $6.29
    • 10 $6.29
    • 100 $6.29
    • 1000 $6.29
    • 10000 $6.29
    Get Quote

    Cypress Semiconductor CY7C1313TV18-167BZC

    CY7C1313TV18-167BZC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical CY7C1313TV18-167BZC 1,091 25
    • 1 -
    • 10 -
    • 100 $43.04
    • 1000 $38.50
    • 10000 $36.24
    Buy Now
    Rochester Electronics CY7C1313TV18-167BZC 1,311 1
    • 1 -
    • 10 -
    • 100 $34.43
    • 1000 $30.80
    • 10000 $28.99
    Buy Now

    Cypress Semiconductor CY7C1313AV18-200BZC

    CY7C1313AV18-200BZC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical CY7C1313AV18-200BZC 756 25
    • 1 -
    • 10 -
    • 100 $21.54
    • 1000 $19.27
    • 10000 $18.14
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    Bristol Electronics CY7C1313AV18-200BZC 126
    • 1 -
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    • 10000 -
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    Rochester Electronics CY7C1313AV18-200BZC 780 1
    • 1 -
    • 10 -
    • 100 $17.23
    • 1000 $15.42
    • 10000 $14.51
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    Cypress Semiconductor CY7C1313V18-200BZC

    CY7C1313V18-200BZC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical CY7C1313V18-200BZC 341 25
    • 1 -
    • 10 -
    • 100 $26.51
    • 1000 $23.73
    • 10000 $22.32
    Buy Now
    Quest Components () CY7C1313V18-200BZC 50
    • 1 $20.55
    • 10 $20.55
    • 100 $19.76
    • 1000 $19.76
    • 10000 $19.76
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    CY7C1313V18-200BZC 4
    • 1 $31.62
    • 10 $31.62
    • 100 $31.62
    • 1000 $31.62
    • 10000 $31.62
    Buy Now
    Rochester Electronics CY7C1313V18-200BZC 341 1
    • 1 -
    • 10 -
    • 100 $21.21
    • 1000 $18.98
    • 10000 $17.86
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    CY7C1313 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CY7C1311CV18

    Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
    Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original
    cy7c1311cv18cy7c1911cv18cy7c1313cv18cy7c1315cv18+118-mbit PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+218-mbit300-mhz PDF

    Contextual Info: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled


    Original
    cy7c1311cv18cy7c1911cv18cy7c1313cv18cy7c1315cv18+318-mbit300-mhz600mhz PDF

    CY7C1311V18

    Abstract: CY7C1313V18 CY7C1315V18
    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • Four-word Burst for reducing address bus frequency


    Original
    cy7c1311v18cy7c1313v18cy7c1315v1818-mb+2250-mhzcy7c1311v18/cy7c1313v18/cy7c1315v18 PDF

    3N50

    Abstract: CY7C1311V18 CY7C1313V18 CY7C1315V18
    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    cy7c1311v18cy7c1313v18cy7c1315v1818-mbit+2250-mhz3n50 PDF

    Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+118-mbit PDF

    CY7C1311V18

    Abstract: CY7C1313V18 CY7C1315V18
    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    cy7c1311v18cy7c1313v18cy7c1315v1818-mbit+1250-mhz PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+218-mbit300-mhz PDF

    CY7C13X

    Abstract: CY7C1311V18 CY7C1313V18 CY7C1315V18 BB165 CY7C1313
    Contextual Info: 311V18 CY7C1311V18 CY7C1313V18 CY7C1315V18 ADVANCE INFORMATION 18-Mb 4-Word Burst SRAM with QDR -II ArchitecFeatures Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 300-MHz Clock for High Bandwidth


    Original
    311v18cy7c1311v18cy7c1313v18cy7c1315v18+618-mb300-mhzcy7c1311v18/cy7c1313v18/cy7c1315v18cy7c13xbb165cy7c1313 PDF

    Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+518-mbit300-mhz600mhzseleccy7c1911bv18278-mhz PDF

    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    cy7c1311v18cy7c1313v18cy7c1315v1818-mb+2250-mhzpage10 PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+1cy7c1315kv18 PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+1cy7c1315kv18 PDF

    CY7C1311AV18

    Abstract: CY7C1313AV18 CY7C1315AV18
    Contextual Info: CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    cy7c1311av18cy7c1313av18cy7c1315av1818-mb+2250-mhzcy7c1311av18/cy7c1313av18/cy7c1315av18 PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1311KV18 – 2 M x 8 ■ 333-MHz clock for high bandwidth


    Original
    18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+2cy7c1315kv18333-mhz PDF

    Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-07165 Spec Title: 7C1313CV18/CY7C1315CV18, 18-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture


    Original
    7c1313cv18/cy7c1315cv1818-mbitcy7c1313cv18cy7c1315cv18 PDF

    Contextual Info: CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1311JV18 – 2M x 8 ■ 300 MHz Clock for High Bandwidth


    Original
    cy7c1311jv18/cy7c1911jv18cy7c1313jv18/cy7c1315jv1818-mbitcy7c1311jv18+2cy7c1313jv18cy7c1315jv18 PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+118-mbit PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    cy7c1311kv18cy7c1911kv18cy7c1313kv18cy7c1315kv18+218-mbit333-mhz PDF

    Contextual Info: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 •


    Original
    cy7c1313cv18cy7c1315cv1818-mbit PDF

    CY7C1911BV18

    Abstract: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1313
    Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+218-mbitcy7c1313 PDF

    Contextual Info: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    cy7c1311bv18cy7c1313bv18cy7c1315bv1818-mbit+5300-mhz600mhzcy7c1911bv18bb165ebb165d PDF

    CY7C1311CV18

    Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
    Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original
    cy7c1311cv18cy7c1911cv18cy7c1313cv18cy7c1315cv18+118-mbit PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+1cy7c1315kv18 PDF