CY7C1313 Search Results
CY7C1313 Datasheets (55)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| CY7C131-30JC | Cypress Semiconductor | 1K x 8 Dual-Port Static Ram | Original | 310.89KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30JC | Cypress Semiconductor | 1024 x 8 Dual-Port Static RAM | Scan | 911.34KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30JC | Cypress Semiconductor | 1K x 8 Dual-Port Static RAM | Scan | 415.46KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30JI | Cypress Semiconductor | 1K x 8 Dual-Port Static Ram | Original | 310.89KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30JI | Cypress Semiconductor | 1024 x 8 Dual-Port Static RAM | Scan | 911.34KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30JI | Cypress Semiconductor | 1K x 8 Dual-Port Static RAM | Scan | 415.46KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30LC | Cypress Semiconductor | 1024 x 8 Dual-Port Static RAM | Scan | 911.34KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30NC | Cypress Semiconductor | 1K x 8 Dual-Port Static Ram | Original | 310.89KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-30NC | Cypress Semiconductor | 1K x 8 Dual-Port Static RAM | Scan | 415.46KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35FMB | Cypress Semiconductor | 1024 x 8 Dual-Port Static RAM | Scan | 911.34KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35JC | Cypress Semiconductor | 1K x 8 Dual-Port Static Ram | Original | 310.89KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35JC | Cypress Semiconductor | 1024 x 8 Dual-Port Static RAM | Scan | 911.34KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35JC | Cypress Semiconductor | Multiple Array MatriX High-Density EPLDs | Scan | 920.78KB | 12 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35JC | Cypress Semiconductor | 1K x 8 Dual-Port Static RAM | Scan | 415.46KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35JI | Cypress Semiconductor | 1K x 8 Dual-Port Static Ram | Original | 310.89KB | 16 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35JI | Cypress Semiconductor | 1024 x 8 Dual-Port Static RAM | Scan | 911.34KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35JI | Cypress Semiconductor | 1K x 8 Dual-Port Static RAM | Scan | 415.46KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35LC | Cypress Semiconductor | 1024 x 8 Dual-Port Static RAM | Scan | 911.34KB | 13 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35LC | Cypress Semiconductor | Multiple Array MatriX High-Density EPLDs | Scan | 920.78KB | 12 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| CY7C131-35LMB | Cypress Semiconductor | Multiple Array MatriX High-Density EPLDs | Scan | 920.78KB | 12 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CY7C1313 Price and Stock
Infineon Technologies AG CY7C1313KV18-250BZXIIC: SRAM memory; 18MbSRAM; 1Mx18bit; FBGA165; parallel; -40÷85°C |
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CY7C1313KV18-250BZXI | 136 |
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CY7C1313KV18-250BZXI | Tray | 272 |
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CY7C1313KV18-250BZXI | 1,585 | 1 |
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CY7C1313KV18-250BZXI | 49 |
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Infineon Technologies AG CY7C1313KV18-250BZCSRAM Chip Sync Dual 1.8V 18M-bit 1M x 18 0.45ns 165-Pin FBGA Tray |
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CY7C1313KV18-250BZC | 1,360 | 1,360 |
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CY7C1313KV18-250BZC | Tray | 680 |
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CY7C1313KV18-250BZC | 82 | 1 |
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CY7C1313KV18-250BZC | 1,777 |
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Cypress Semiconductor CY7C1313TV18-167BZCCY7C1313TV18-167BZC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY7C1313TV18-167BZC | 1,091 | 25 |
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| CY7C1313TV18-167BZC | 220 | 25 |
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CY7C1313TV18-167BZC | 1,311 | 1 |
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Cypress Semiconductor CY7C1313AV18-200BZCCY7C1313AV18-200BZC |
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CY7C1313AV18-200BZC | 756 | 25 |
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CY7C1313AV18-200BZC | 126 |
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CY7C1313AV18-200BZC | 780 | 1 |
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Cypress Semiconductor CY7C1313V18-200BZCCY7C1313V18-200BZC |
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CY7C1313V18-200BZC | 341 | 25 |
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CY7C1313 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
CY7C1311CV18
Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
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Original |
cy7c1311cv18cy7c1911cv18cy7c1313cv18cy7c1315cv18+1 | |
CY7C1311BV18
Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
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Original |
cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+2 | |
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Contextual Info: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled |
Original |
cy7c1311cv18cy7c1911cv18cy7c1313cv18cy7c1315cv18+3 | |
CY7C1311V18
Abstract: CY7C1313V18 CY7C1315V18
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Original |
cy7c1311v18cy7c1313v18cy7c1315v1818-mb+2 | |
3N50
Abstract: CY7C1311V18 CY7C1313V18 CY7C1315V18
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Original |
cy7c1311v18cy7c1313v18cy7c1315v1818-mbit+2 | |
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Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+1 | |
CY7C1311V18
Abstract: CY7C1313V18 CY7C1315V18
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Original |
cy7c1311v18cy7c1313v18cy7c1315v1818-mbit+1 | |
CY7C1311BV18
Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
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Original |
cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+2 | |
CY7C13X
Abstract: CY7C1311V18 CY7C1313V18 CY7C1315V18 BB165 CY7C1313
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Original |
311v18cy7c1311v18cy7c1313v18cy7c1315v18+6 | |
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Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth |
Original |
cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+5 | |
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Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency |
Original |
cy7c1311v18cy7c1313v18cy7c1315v1818-mb+2 | |
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Contextual Info: CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+1 | |
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Contextual Info: CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+1 | |
CY7C1311AV18
Abstract: CY7C1313AV18 CY7C1315AV18
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Original |
cy7c1311av18cy7c1313av18cy7c1315av1818-mb+2 | |
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Contextual Info: CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1311KV18 – 2 M x 8 ■ 333-MHz clock for high bandwidth |
Original |
18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+2 | |
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Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-07165 Spec Title: 7C1313CV18/CY7C1315CV18, 18-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture |
Original |
7c1313cv18/cy7c1315cv1818-mbitcy7c1313cv18cy7c1315cv18 | |
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Contextual Info: CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1311JV18 – 2M x 8 ■ 300 MHz Clock for High Bandwidth |
Original |
cy7c1311jv18/cy7c1911jv18cy7c1313jv18/cy7c1315jv1818-mbitcy7c1311jv18+2 | |
CY7C1311BV18
Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
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Original |
cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+1 | |
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Contextual Info: CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
cy7c1311kv18cy7c1911kv18cy7c1313kv18cy7c1315kv18+2 | |
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Contextual Info: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 • |
Original |
cy7c1313cv18cy7c1315cv1818-mbit | |
CY7C1911BV18
Abstract: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1313
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Original |
cy7c1311bv18cy7c1911bv18cy7c1313bv18cy7c1315bv18+2 | |
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Contextual Info: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth |
Original |
cy7c1311bv18cy7c1313bv18cy7c1315bv1818-mbit+5 | |
CY7C1311CV18
Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
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Original |
cy7c1311cv18cy7c1911cv18cy7c1313cv18cy7c1315cv18+1 | |
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Contextual Info: CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions |
Original |
18-mbitcy7c1311kv18cy7c1911kv18cy7c1313kv18+1 | |