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    CY7C1313 Search Results

    CY7C1313 Datasheets (55)

    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    CY7C131-30JC
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-30JC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-30JC
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-30JI
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-30JI
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-30JI
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-30LC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-30NC
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-30NC
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-35FMB
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35JC
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-35JC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35JC
    Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF 920.78KB 12
    CY7C131-35JC
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-35JI
    Cypress Semiconductor 1K x 8 Dual-Port Static Ram Original PDF 310.89KB 16
    CY7C131-35JI
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35JI
    Cypress Semiconductor 1K x 8 Dual-Port Static RAM Scan PDF 415.46KB 13
    CY7C131-35LC
    Cypress Semiconductor 1024 x 8 Dual-Port Static RAM Scan PDF 911.34KB 13
    CY7C131-35LC
    Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF 920.78KB 12
    CY7C131-35LMB
    Cypress Semiconductor Multiple Array MatriX High-Density EPLDs Scan PDF 920.78KB 12
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    CY7C1313 Price and Stock

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    Infineon Technologies AG CY7C1313KV18-250BZXI

    IC SRAM 18MBIT PAR 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1313KV18-250BZXI Tray 98 1
    • 1 $32.13
    • 10 $29.72
    • 100 $28.06
    • 1000 $28.06
    • 10000 $28.06
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    Avnet Americas () CY7C1313KV18-250BZXI Tray 39
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    • 100 $18.00
    • 1000 $17.48
    • 10000 $17.48
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    CY7C1313KV18-250BZXI Tray 11 Weeks 272
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    Flip Electronics CY7C1313KV18-250BZXI 49
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    Cypress Semiconductor CY7C1313KV18-250BZC

    NO WARRANTY
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    DigiKey CY7C1313KV18-250BZC Tray 20 1
    • 1 $6.82
    • 10 $6.35
    • 100 $6.35
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    • 10000 $6.35
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    Rochester Electronics CY7C1313KV18-250BZC 262 1
    • 1 -
    • 10 -
    • 100 $21.08
    • 1000 $18.86
    • 10000 $17.75
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    Rochester Electronics LLC CY7C1313V18-200BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1313V18-200BZC Bulk 13
    • 1 -
    • 10 -
    • 100 $23.22
    • 1000 $23.22
    • 10000 $23.22
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    Infineon Technologies AG CY7C1313CV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1313CV18-250BZC Tray 136
    • 1 -
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    • 100 -
    • 1000 $33.65
    • 10000 $33.65
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    Rochester Electronics LLC CY7C1313CV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1313CV18-250BZC Tray 10
    • 1 -
    • 10 $33.05
    • 100 $33.05
    • 1000 $33.05
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    CY7C1313 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    CY7C1311CV18

    Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
    Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original
    CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 PDF

    Contextual Info: CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports • QDR-II operates with 1.5 cycle read latency when the DLL is enabled


    Original
    CY7C1311CV18 CY7C1911CV18 CY7C1313CV18 CY7C1315CV18 18-Mbit 300-MHz 600MHz) PDF

    CY7C1311V18

    Abstract: CY7C1313V18 CY7C1315V18
    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • Four-word Burst for reducing address bus frequency


    Original
    CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb 250-MHz CY7C1311V18/CY7C1313V18/CY7C1315V18 CY7C1311V18 CY7C1313V18 CY7C1315V18 PDF

    3N50

    Abstract: CY7C1311V18 CY7C1313V18 CY7C1315V18
    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit 250-MHz 3N50 CY7C1311V18 CY7C1313V18 CY7C1315V18 PDF

    Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit CY7C1911BV18, CY7C1315BV18 PDF

    CY7C1311V18

    Abstract: CY7C1313V18 CY7C1315V18
    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mbit 250-MHz CY7C1311V18 CY7C1313V18 CY7C1315V18 PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 PDF

    CY7C13X

    Abstract: CY7C1311V18 CY7C1313V18 CY7C1315V18 BB165 CY7C1313
    Contextual Info: 311V18 CY7C1311V18 CY7C1313V18 CY7C1315V18 ADVANCE INFORMATION 18-Mb 4-Word Burst SRAM with QDR -II ArchitecFeatures Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 300-MHz Clock for High Bandwidth


    Original
    311V18 CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb 300-MHz CY7C1311V18/CY7C1313V18/CY7C1315V18 CY7C13X CY7C1311V18 CY7C1313V18 CY7C1315V18 BB165 CY7C1313 PDF

    Contextual Info: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz 600MHz) SelecCY7C1911BV18 278-MHz PDF

    Contextual Info: CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    CY7C1311V18 CY7C1313V18 CY7C1315V18 18-Mb 250-MHz Page10) PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 PDF

    CY7C1311AV18

    Abstract: CY7C1313AV18 CY7C1315AV18
    Contextual Info: CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY 18-Mb QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency


    Original
    CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 18-Mb 250-MHz CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1311KV18 – 2 M x 8 ■ 333-MHz clock for high bandwidth


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 333-MHz PDF

    Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-07165 Spec Title: 7C1313CV18/CY7C1315CV18, 18-MBIT QDR R II SRAM 4-WORD BURST ARCHITECTURE Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture


    Original
    7C1313CV18/CY7C1315CV18, 18-MBIT CY7C1313CV18 CY7C1315CV18 PDF

    Contextual Info: CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1311JV18 – 2M x 8 ■ 300 MHz Clock for High Bandwidth


    Original
    CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit CY7C1311JV18 CY7C1313JV18 CY7C1315JV18 PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit CY7C1311KV18 333-MHz CY7C1313KV18 PDF

    Contextual Info: CY7C1313CV18 CY7C1315CV18 18-Mbit QDR II SRAM 4-Word Burst Architecture 18-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1313CV18 – 1M x 18 •


    Original
    CY7C1313CV18 CY7C1315CV18 18-Mbit CY7C1313CV18 PDF

    CY7C1911BV18

    Abstract: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1313
    Contextual Info: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit CY7C1911BV18 CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1313 PDF

    Contextual Info: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz 600MHz) CY7C1911BV18 BB165E BB165D PDF

    CY7C1311CV18

    Abstract: CY7C1313CV18 CY7C1315CV18 CY7C1911CV18
    Contextual Info: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth ■


    Original
    CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit CY7C1311CV18 CY7C1313CV18 CY7C1311CV18 CY7C1313CV18 CY7C1315CV18 CY7C1911CV18 PDF

    Contextual Info:  CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 18-Mbit QDR II SRAM Four-Word Burst Architecture 18-Mbit QDR® II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    18-Mbit CY7C1311KV18, CY7C1911KV18 CY7C1313KV18, CY7C1315KV18 CY7C1311KV18 CY7C1911KV18 CY7C1313KV18 PDF