GS81302TXX Search Results

Contextual Info: Preliminary GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: Preliminary GS81302T07/10/19/37E-400/375/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface

Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

CQ 765

Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

GS81302T36GE-333

Contextual Info: Preliminary GS81302T08/09/18/36E-333/300/250/200/167 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: Preliminary GS81302T08/09/18/36E-333/300/250/200/167 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: Preliminary GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface

Contextual Info: Preliminary GS81302T08/09/18/36E-333/300/250/200/167 144Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

GS81302T18GE-333

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package • Double Data Rate interface

AN1019

Contextual Info: AN1019 SigmaQuad-II+ and SigmaDDR-II+ On-Die Termination ODT Introduction When an electrical signal is transmitted along a transmission line, it is reflected back when it reaches the end of the line. That reflection induces noise which adversely affects the quality of the signal, thereby making it more difficult for the receiving device

Contextual Info: Preliminary GS81302T06/11/20/38E-450/400/375/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface

Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus

Contextual Info: Preliminary GS81302T19/37E-400/375 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaCIO DDR-II+ Burst of 2 SRAM 400 MHz–375 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

Contextual Info: Preliminary GS81302T08/09/18/36E-333/300/267/250/200/167 144Mb SigmaCIO DDR-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaCIO Interface • Common I/O bus

GS81302T19E-400

Abstract: tms 375
Contextual Info: Preliminary GS81302T07/10/19/37E-400/375/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface