GS81302T1937 Search Results
GS81302T1937 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
---|---|---|---|
Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package |
Original |
GS81302T07/10/19/37E-450/400/350/333/300 144Mb 165-Bump GS81302T1937 | |
CQ 765Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package |
Original |
GS81302T07/10/19/37E-450/400/350/333/300 144Mb 165-Bump GS81302T1937 CQ 765 | |
Contextual Info: Preliminary GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface |
Original |
GS81302T07/10/19/37E-450/400/350/333/300 165-Bump 165-bump, GS81302T1937 | |
Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package |
Original |
GS81302T07/10/19/37E-450/400/350/333/300 144Mb 165-Bump GS81302T1937 | |
Contextual Info: GS81302T07/10/19/37E-450/400/350/333/300 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 450 MHz–300 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus |
Original |
GS81302T07/10/19/37E-450/400/350/333/300 165-Bump 165-bump, GS81302T1937 |