CPRS Search Results

AD95100

Abstract: Pulling VCXO ad9510 500 Series VCXO ad9510 jedec package MO-220 64-led AD9510 ADF4106 TCO-2112 1448H TCO TOYOCOM AD9510BCPZ
Contextual Info: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES VS GND RSET CPRSET VCP DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION AD9510 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL SETTINGS CP STATUS CLK2 CLK2B

500 Series VCXO ad9510

Contextual Info: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES VS GND RSET CPRSET VCP DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION AD9510 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL SETTINGS CP STATUS CLK2 CLK2B

TCO-2112

Abstract: AD9516
Contextual Info: 14-Output Clock Generator AD9516-5 FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

LSI21002

Abstract: LSI53C895 LSI53C896 S14007 68pin TO 50 PIN SCSI adapter S14001A Bios error code fc00
Contextual Info: USER’S GUIDE LSI21002 PCI to Dual Channel SCSI Host Adapter Version 1.1 November 2000 S14001.A Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: 1. 2. This device may not cause harmful interference, and

LSI22802

Abstract: scsi pinout LSI53C875 LSI53C876 LSI53C895 LSI8751D LSIU40HVD S14007
Contextual Info: USER’S GUIDE LSIU40HVD PCI to Dual Channel SCSI Host Adapter August 2002 Version 2.2 DB15-000101-02 Electromagnetic Compatibility Notices This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: 1. 2. This device may not cause harmful interference, and

VFP9-S

Abstract: CP15 ARM Architecture Reference Manual VFP9S 0x00000000b
Contextual Info: VFP9-S Vector Floating-point Coprocessor r0p2 Technical Reference Manual Copyright 2002, 2003 ARM Limited. All rights reserved. ARM DDI 0238B VFP9-S r0p2 Vector Floating-point Coprocessor Technical Reference Manual Copyright © 2002, 2003 ARM Limited. All rights reserved.

Contextual Info: HD68230-PI/T Parallel Interface Timer -P R E L IM IN A R Y The HD68230 Parallel Interface/Timer provides versatile double buffered parallel interfaces and an operating system oriented timer to HD68000 systems. The parallel interfaces operate in

Contextual Info: APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

em 329

Abstract: XC68F333CFT16 M68000 MC68F333 YFF700 YFF702 YFF706 YFF710 UPC 494 Application Note upc uninterrupted power supply circuit diagram
Contextual Info: MC68F333 USER’S MANUAL Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and

11-B

Abstract: DS31256 DS3134 SV54
Contextual Info: DEMO KIT AVAILABLE DS31256 Envoy 256-Channel, High-Throughput HDLC Controller www.maxim-ic.com GENERAL DESCRIPTION The DS31256 Envoy is a 256-channel HDLC controller capable of handling up to 64 T1 or E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four

SPMC02A

Abstract: sunplus mcu 000D 00FF 27C256 ic 741 working as comparator TM2-V
Contextual Info: SPMC02A MICROCONTROLLER GENERAL DESCRIPTION FEATURES SUNPLUS SPMC02A contains a SUNPLUS 8 bit Micro-Controller Built-in 8-bit Sunplus CPU core and up to 6.0MHz clock Units MCU , 4.5K bytes ROM, 128 bytes SRAM and 2 8-bit operation Timers. 128 bytes SRAM The advanced sub-micron CMOS process technology

ALNUP+161609

Contextual Info: HAMMOND MANUFACTURING CO. INC. 475 Cayuga Rd., Suite 100 Cheektowaga, NY 14225 Tel: 716 630-7030 Fax: (716) 630-7042 www.hammondmfg.com Manufacturer’s Suggested U.S. Resale Pricing Transformers & Inductors Small Enclosures Outlet Strips Electrical Enclosures

CA20C03A

Contextual Info: CA20C03A DES ENCRYPTION PROCESSOR • The CA20C03A is an improved version of the DES encryption processor designed by Tundra Semiconductor Corporation. • Data transfer rates up to 3.85 Mbytes per second • Encrypt and decrypt using Data Encryption Standard DES adopted by the U.S. Department

nicd 1.2v battery

Abstract: MAX847 MAX847EEI MAX847EVKIT
Contextual Info: 19-1349; Rev 1a; 10/98 L MANUA ION KIT HEET T A U L EVA TA S WS DA FOLLO 1-Cell, Step-Up Two-Way Pager System IC _Features ♦ 80mA Output from 1 Cell at 90% Efficiency ♦ 13µA Idle Mode coast Current ♦ Selectable Low-Noise PWM or Low-Current

cbb22

Contextual Info: HAMMOND MANUFACTURING CO. LTD. 394 Edinburgh Road North Guelph, Ontario N1H 1E5 Tel: 519 822-2960 Fax: (519) 822-0715 www.hammondmfg.com Manufacturer’s Suggested Canadian Resale Pricing Transformers & Inductors Small Enclosures Outlet Strips Electrical Enclosures

Tco 2112 245.76 MHz

Abstract: TCO-2112 ADF4106 AD9511 Rev a
Contextual Info: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs AD9511 FEATURES FUNCTIONAL BLOCK DIAGRAM VS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

CONTROLLER

Abstract: speed control of three phase ac induction motor 3 phase ac Induction motor speed controller ic SPEED CONTROLLER FOR SMALL MOTOR WITH TACHOGENERATOR 220v dc motor speed control circuit 220v DC MOTOR SPEED CONTROLLER 220v DC MOTOR SPEED CONTROLLER schematic cmos XOR schmitt trigger pwm based bidirectional dc motor speed SCHEMATIC 12 to 220v inverter
Contextual Info: ST92141 8/16-BIT MCU FOR 3-PHASE AC MOTOR CONTROL • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW, HALT and STOP modes 0-25 MHz Operation internal clock @ 5V±10%

Contextual Info: LTC6945 Ultralow Noise and Spurious 0.35GHz to 6GHz Integer-N Synthesizer DESCRIPTION FEATURES n n n n n n n n n n n n n n Low Noise Integer-N PLL 350MHz to 6GHz VCO Input Range –226dBc/Hz Normalized In-Band Phase Noise Floor –274dBc/Hz Normalized In-Band 1/f Noise

Contextual Info: 6-Output Clock Generator with Integrated 1.6 GHz VCO AD9518-4 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation

Contextual Info: APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

ic74lvc541apw

Abstract: INDL0805 CNHEC0470-01-630 AD9522 HC49SD R92 vs R94 R5562
Contextual Info: 1 2 3 4 REVISIONS SOME TERMINATION COMPONENTS ARE OPTIONAL ONLY. REFER TO BOM S FOR TYPICALCOMPONENT INSTALLATION INFORMATION. OUT1 C6 VS C56 .1UF C58 .1UF C59 .1UF C67 .1UF .1UF C65 C75 C70 .1UF A C14 0.1UF .1UF .1UF R80 C5 .1UF INITIAL RELEASE R83 C92 200

CP-64-4

Contextual Info: APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

frequency divider

Contextual Info: 12-Output Clock Generator with Integrated 2.5 GHz VCO AD9517-1 APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Contextual Info: FUNCTIONAL BLOCK DIAGRAM CP REF1 REFIN REF2 CLK LF STATUS MONITOR PLL Low phase noise, phase-locked loop PLL On-chip VCO tunes from 1.75 GHz to 2.25 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability