AD9510 Search Results

TCO-2112T

Abstract: R904 74LVC14A AD9510 C108 C109 CY7C68013 three phase distribution panel schematic EB056 R1483
Contextual Info: Evaluation Board for AD9510 AD9510/PCB FEATURES AD9510 DEVICE DESCRIPTION Full-featured evaluation board for the AD9510 PC evaluation software for control and exercise of the AD9510 USB interface The AD9510 provides a multi-output clock distribution function along with an on-chip phase-locked loop PLL

AD9510

Contextual Info: AD9510 Datasheet Comparison to ADIsimCLK CLK INPUT = 622.08MHz File: AD9510_622_08_LVPECL_LVDS.clk In this design file the ADIsimCLK predicted performance for the AD9510, 1.2GHz, 8-channel Clock Distribution IC is compared to actual measured lab results. Graphs are provided which plot both

Contextual Info: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES VS GND RSET CPRSET VCP DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION AD9510 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL SETTINGS CP STATUS CLK2 CLK2B

AD95100

Abstract: Pulling VCXO ad9510 500 Series VCXO ad9510 jedec package MO-220 64-led AD9510 ADF4106 TCO-2112 1448H TCO TOYOCOM AD9510BCPZ
Contextual Info: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES VS GND RSET CPRSET VCP DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION AD9510 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL SETTINGS CP STATUS CLK2 CLK2B

ic501

Abstract: RVD1SS133TA RVSGP2S24BC XLJ93LC46A 2SD2374PQAU MA165TA KSD471ACYGTA an7357fb AN7356SC-E2 mtzj6r2bta
Contextual Info: O RDER NO. AD9510251S5 A2 Service Manual Cassette Deck Dolby NR-Equipped Stereo Double Cassette Deck RS-TR474 Colour D O L B Y B «C N R H X P R O <K .Black Type Area Suffix for Model No. * Dolby noise reduction and HX Pro headroom extension m anufactured under license from Dolby Laboratories

AD9510

Abstract: AD9540 ADF4106
Contextual Info: Preliminary Technical Data 800 MHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump CP current

AD9510

Abstract: oe33 Pulling VCXO ad9510 ADF4106 AN-501 AN-586
Contextual Info: Preliminary Technical Data 800 MHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump CP current

AD9510

Abstract: 61,44MHZ
Contextual Info: AD9510 Datasheet Comparison to ADIsimCLK CLK INPUT = 245.76MHz File: AD9510_245_76_LVPECL_LVDS_CMOS.clk In this design file the ADIsimCLK predicted performance for the AD9510, 1.2GHz, 8-channel Clock Distribution IC is compared to actual measured lab results. Graphs are provided which plot both

500 Series VCXO ad9510

Contextual Info: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs AD9510 FEATURES VS GND RSET CPRSET VCP DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION AD9510 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL SETTINGS CP STATUS CLK2 CLK2B

AD9510

Abstract: ASIC2
Contextual Info: 9510_quick_start.clk Design Example Description a In this design the AD9510, 1.2GHz, 8-Channel Clock Distribution IC is used to provide clocks to analog-todigital converters ADCs , digital-to-analog converters (DACs) and digital application specific integrated circuits

AD9510

Contextual Info: AD9510 Datasheet Comparison to ADIsimCLK CLK INPUT = 491.52MHz File: AD9510_491_52_LVPECL_LVDS.clk In this design file the ADIsimCLK predicted performance for the AD9510, 1.2GHz, 8-channel Clock Distribution IC is compared to actual measured lab results. Graphs are provided which plot both

LC1210

Abstract: PIC H501 OSC500 ic c575 diagram SMDC110F K3638 SMDC110F-2 adc c520 cd 1691 cp cp c531
Contextual Info: 12位, 80 MSPS/105 MSPS/125 MSPS, 18V模数转换器 AD9233 功能框图 特性 应用 超声设备 中频采样的通信接收机 IS-95CDMA-One、IMT-2000 电池供电仪表 手持式示波仪 低成本数字示波器 概述 AD9233是一款单芯片、12位、80 MSPS/ 105 MSPS/125 MSPS

max9291

Abstract: AD6643-200 CP-64-4 901MH AN83-5 10-com 1401M 10True
Contextual Info: Dual IF Receiver AD6643 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND DRVDD AD6643 VIN+A VIN–A PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 VCM VIN+B VIN–B PIPELINE ADC 14 NOISE SHAPING REQUANTIZER 11 DATA MULTIPLEXER AND LVDS DRIVERS DCO± D0±

17D06

Abstract: 16D06 D01N
Contextual Info: FEATURES APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Handheld scope meters

AD9250

Abstract: E19 CORE TRANSFORMER AD9524 upstream docsis cmts JESD204B
Contextual Info: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9250 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM DVDD AGND DGND DRGND AD9250 VIN+A VIN–A PIPELINE 14-BIT ADC VCM VIN+B VIN–B PIPELINE 14-BIT ADC JESD-204B INTERFACE SERDOUT0± CML, TX

956d

Abstract: AD9258 D15A AD9269-40EBZ 765D
Contextual Info: 16-Bit, 20/40/65/80 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9269 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V to 3.3 V output supply Integrated quadrature error correction QEC SNR 77.6 dBFS at 9.7 MHz input 71 dBFS at 200 MHz input

max8895

Abstract: AD9613BCPZ-250
Contextual Info: FEATURES SNR = 69.6 dBFS at 185 MHz fIN and 250 MSPS SFDR = 86 dBc at 185 MHz fIN and 250 MSPS −149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 770 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs

AD9467

Abstract: B0205F5050A00 AD520* differential amplifier
Contextual Info: 16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter AD9467 Data Sheet 75.5 dBFS SNR to 210 MHz at 250 MSPS 90 dBFS SFDR to 300 MHz at 250 MSPS SFDR at 170 MHz at 250 MSPS 92 dBFS at −1 dBFS 100 dBFS at −2 dBFS 60 fs rms jitter Excellent linearity at 250 MSPS

circuit diagram of analog clock using logic gates

Contextual Info: FEATURES SNR = 70.6 dBFS at 185 MHz AIN and 250 MSPS SFDR = 85 dBc at 185 MHz AIN and 250 MSPS −151.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS Total power consumption: 785 mW at 250 MSPS 1.8 V supply voltages LVDS ANSI-644 levels outputs

AD9639

Abstract: s31 schottky diode mdac s29 proportional controller 2812 AN-827 AN-835 JESD204 Packaging Top Mark LFCSP AD9516 generic JESD204 radar
Contextual Info: Quad, 12-Bit, 170 MSPS/210 MSPS Serial Output 1.8 V ADC AD9639 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9639 VIN + A VIN – A BUF SHA BUF SHA BUF SHA BUF SHA DOUT + A PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC 12 VCM A VIN + B

smd diode c644

Abstract: diode c649 smd diode c548 C748 SMC transistor C734 smd diode c549 C706 diode c624 DIODE smd diode C645 diode c741
Contextual Info: Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter AD9222 8 ADCs integrated into 1 package 93 mW ADC power per channel at 50 MSPS SNR = 70 dB to Nyquist ENOB = 11.3 bits SFDR = 84 dBc Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical)

an-877application

Contextual Info: 16-Bit, 125 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9268 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 78.2 dBFS @ 70 MHz SFDR = 88 dBc @ 70 MHz Low power: 750 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider

center tap transformer 18 0 18

Abstract: C532 diode 6562D 9018D
Contextual Info: Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter AD9259 4 ADCs integrated into 1 package 98 mW ADC power per channel at 50 MSPS SNR = 73 dB to Nyquist ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity DNL = ±0.5 LSB (typical) INL = ±1.5 LSB (typical)

AD9258BCPZ-125

Abstract: AD9258-105 AD9258 850dBc AD9258-125
Contextual Info: 14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter ADC AD9258 FEATURES APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems