DDR PHY ASIC
Abstract: MIPS64 RM9000x2
Contextual Info: RM9222 RM9000x2GL Preliminary RM9222 RM9000x2GL Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9222 RM9000x2GL Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPSbased RM9000 Family processors by providing features specifically suited for
|
Original
|
rm9222rm9000x2glrm9000pmc-2021862+3ddr phy asicmips64rm9000x2
|
PDF
|
corelis controller
Abstract: MIPS64 ethernet mac
Contextual Info: RM9222 Released RM9222 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9222 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:
|
Original
|
rm9222gpi-8/16pmc-2021862corelis controller+2mips64ethernet mac
|
PDF
|
|
Contextual Info: RM9100A Released AM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A
|
Original
|
rm9100ae900064-bitrm9200a+416-kbyte256-kbyte64-entrypmc-2040955
|
PDF
|
ddr ram
Contextual Info: RM9222 Preliminary RM9222 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9222 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:
|
Original
|
rm9222gpi-8/16pmc-2021862ddr ram |
PDF
|
l2 cache design in verilog
Abstract: 476FP tag l2 ibm+powerpc+476fp powerpc 476FP
Contextual Info: A high-performance, on-chip system bus that supports coherency in multiple-core designs IBM CoreConnect PLB6 On-Chip System Bus Architectural features Highlights Support for concurrent traffic on read and write data buses Support for concurrent transfers on all segments
|
Original
|
128-bitl2 cache design in verilog476fptag l2+2ibm+powerpc+476fppowerpc 476fp
|
PDF
|
PR2000
Abstract: PR3000A MIPS R3000A R2000 mips processor
Contextual Info: PERFORMANCE INTEGRATED MIPS MODULE PIMM” FEATURES: • • bus snooper to assist In maintaining cache coherency in multiprocessor systems Single VLSI multichip module contains: • PR3000A CPU • PR3010A FPA ■ P4C92815 x4 Bicameral SCRAM contains: • 32 KBytes each of address latched
|
OCR Scan
|
pr3000apr3010apr3100ap4c92815+640mhz144-pinmil-std-883cpr2000mips r3000ar2000 mips processor
|
PDF
|
RM9224
Abstract: DDR PHY ASIC MIPS64 "network interface cards" 896-pin pmc
Contextual Info: RM9224 Released RM9224 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9224 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:
|
Original
|
rm9224pmc-2021863ddr phy asicmips64+2network interface cards896-pin pmc
|
PDF
|
API NETWORKS
Abstract: rm5200 sysad RM9000x2 Integrated Multiprocessor
Contextual Info: RM9000x2 Preliminary RM9000x2 Integrated Multiprocessor FEATURES DUAL CPU CORES CACHE AND I/O COHERENCY The RM9000x2™ Integrated Multiprocessor is PMC-Sierra's next generation high performance MIPS processor. The RM9000x2 follows in the footsteps of the very successful PMC-Sierra
|
Original
|
rm9000x2rm9000x2tmrm7000tmrm5200tm+7mips64tmrm9000rm7000api networksrm5200sysadrm9000x2 integrated multiprocessor
|
PDF
|
Marvell
Abstract: MIPS64 RM9100A RM9200A 64120A 64-ENTRY
Contextual Info: RM9100A Released Integrated Microprocessor FEATURES E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A
|
Original
|
rm9100ae900064-bitrm9200a+716-kbyte256-kbyte64-entrypmc-2040955marvellmips6464120a
|
PDF
|
API NetWorks
Abstract: Marvell MIPS64 RM9200A E9000
Contextual Info: RM9200A Released Integrated Multiprocessor FEATURES DUAL E9000 CORES CACHE AND I/O COHERENCY PMC-Sierra’s RM9200A Integrated Processor is a high performance 64-bit MIPS-based dual-microprocessor with integrated memory and I/O interfaces. Each core provides:
|
Original
|
rm9200ae900064-bit16-kbyte+6256-kbyte64-entrypmc-2040956api networksmarvellmips64
|
PDF
|
|
Contextual Info: RM9224 Preliminary RM9224 Integrated Multiprocessor FEATURES CACHE AND I/O COHERENCY The RM9224 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:
|
Original
|
rm9224pmc-2021863 |
PDF
|
FLOATING POINT Co Processor
Contextual Info: RM9100A Released PM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A
|
Original
|
rm9100a64-bitrm9200ae9000+4mips6416-kbytepmc-2040955floating point co processor
|
PDF
|
Marvell
Abstract: MIPS64 RM9100A RM9200A
Contextual Info: RM9100A Released AM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A
|
Original
|
rm9100ae900064-bitrm9200a+616-kbyte256-kbyte64-entrypmc-2040955marvellmips64
|
PDF
|
RM7000
Abstract: API NETWORKS hypertransport Marvell MIPS64 RM5200
Contextual Info: RM9000x2 Preliminary AM RM9000x2 Integrated Multiprocessor DUAL CPU CORES CACHE AND I/O COHERENCY The RM9000x2™ Integrated Multiprocessor is PMC-Sierra's next generation high performance MIPS processor. The RM9000x2 follows in the footsteps of the very successful PMC-Sierra
|
Original
|
rm9000x2rm9000x2tmrm7000tmrm5200tm+1016-kbyte256-kbytebr8555rm9000rm7000api networkshypertransportmarvellmips64rm5200
|
PDF
|
|
|
Cy7C601
Abstract: D6336 7C605
Contextual Info: CY7C605A r ^ p p rc c SEMICONDUCTOR Features • M ultiprocessing support • Pin-compatible with CY7C604A • Cache coherency protocol modeled af ter IEEE Futurebus • Separate virtual and physical cache tag memories — Each cache tag memory holds 2048
|
OCR Scan
|
cy7c604a32-bit36-bit32-byte+6cy7c605a7c605a7c601cy7c601d63367c605
|
PDF
|
API NETWORKS
Abstract: E9000 Marvell MIPS64 RM9200A
Contextual Info: RM9200A Released AM Integrated Multiprocessor DUAL E9000 CORES CACHE AND I/O COHERENCY PMC-Sierra’s RM9200A Integrated Processor is a high performance 64-bit MIPS-based dual-microprocessor with integrated memory and I/O interfaces. Each core provides: • 1 GHz operating frequency.
|
Original
|
rm9200ae900064-bit16-kbyte+6256-kbyte64-entrypmc-2040956api networksmarvellmips64
|
PDF
|
Marvell
Abstract: MIPS64 RM-90 RM9000x2 Integrated Multiprocessor E9000
Contextual Info: RM9000x1 Preliminary RM9000x1 Integrated Microprocessor FEATURES E9000 CPU CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9000x1 Integrated Processor is a high performance 64-bit MIPS -based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the
|
Original
|
rm9000x1e9000rm9000x1tm64-bit+9rm9000x2tm16-kbyte256-kbyte64-entrypmc-2021479marvellmips64rm-90rm9000x2 integrated multiprocessor
|
PDF
|
marvell ethernet switch
Abstract: Marvell MIPS64
Contextual Info: RM9100 Released RM9100 Integrated Microprocessor FEATURES E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100 Integrated Processor is a high performance 64-bit MIPS -based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9100™
|
Original
|
rm9100e9000rm9100tm64-bit+716-kbyte256-kbyte64-entrypmc-2021479marvell ethernet switchmarvellmips64
|
PDF
|
MC68349FT25A
Abstract: mc68349 users manual TH 9437 MC68349FT25 MC68330 MC68340 MC68349 VT100
Contextual Info: Freescale Semiconductor, Inc. Hardware resets are held off until completion of the current operand transfer in order to maintain operand coherency. The processor resets at the end of the bus cycle in which the last portion of the operand is transferred, or after the bus monitor has timed out. The bus monitor operates for this specific case whether it is enabled or
|
Original
|
sim49mc68349ft25amc68349 users manualth 9437+5mc68349ft25mc68330mc68340mc68349vt100
|
PDF
|
litton cpu
Abstract: MX 232 military multichip litton military mcm cpu MCP-96 cpu guidance litton mcm military mcm I960 mx
Contextual Info: MILITARY MULTICHIP MODULES LITTON GUIDANCE & CONTROL SYSTEMS i960 MC/MX CPU Computers Using Silicon Substrate MCMs • ■ ■ ■ ■ ■ ■ ■ ■ ■ 10-38 MIPs Microminiaturized Computers With Processor, Memory and I/O in Pin-Compatible Multichip
|
Original
|
mcp96mxp-9616-bitrs-232+10mcp-96litton cpumx 232military multichiplittonmilitary mcm cpucpu guidancelitton mcmmilitary mcmi960 mx
|
PDF
|
MC9S08MP16
Abstract: SE161
Contextual Info: Freescale Semiconductor Mask Set Errata MSE9S08MP16_1M84P Rev. 1, 5/2009 Mask Set Errata for Mask 1M84P Introduction This report applies to mask 1M84P for these products: • MC9S08MP16 • MC9S08MP12 MCU Device Mask Set Identification The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and
|
Original
|
mse9s08mp161m84pmc9s08mp16mc9s08mp12+20j27fse161
|
PDF
|
MC9S08MP16
Abstract: MC9S08MP12
Contextual Info: Freescale Semiconductor Mask Set Errata MSE9S08MP16_0M84P Rev. 1, 05/2009 Mask Set Errata for Mask 0M84P Introduction This report applies to mask 0M84P for these products: • MC9S08MP16 • MC9S08MP12 MCU Device Mask Set Identification The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and
|
Original
|
mse9s08mp160m84pmc9s08mp16mc9s08mp12+10j27f
|
PDF
|
uPD30710
Abstract: VR10000 Series VR12000A R12000 mips R2000 mips R2000 mips processor U12754E
Contextual Info: User’s Manual VR10000 Series 64-/32-bit Microprocessor µPD30700 VR10000™ µPD30700L (VR10000L™) µPD30710 (VR12000™) µPD30710A (VR12000A™) µPD30710L (VR12000L™) Document No. U10278EJ4V0UM00 (4th edition) Date Published March 2001 N CP(K)
|
Original
|
vr1000064-/32-bitpd30700vr10000tm+13pd30700lvr10000ltmpd30710vr12000tmpd30710avr12000atmupd30710vr10000 seriesvr12000ar12000 mipsr2000 mipsr2000 mips processoru12754e
|
PDF
|
apn 2054
Abstract: buc ku MPC602 MPC60XBUSRM M-604 MPR601UMU-02 tcn ape MPR603EUM-01 MPC601EC
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MPC60XBUSRM 1/2004 Rev. 0.1 PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.
|
Original
|
mpc60xbusrm32-bitch370apn 2054+7buc kumpc602m-604mpr601umu-02tcn apempr603eum-01mpc601ec
|
PDF
|