CLOCKED Search Results

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

CIRCUIT DIAGRAM OF Bf 199

Contextual Info: TC4042BP/BF/BFN C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4042B QUAD CLOCKED "D " LATCH_ TC4042B contains fo u r circuits o f "D " type latches having common CLOCK input and POLARITY input. W hen POLARITY input is placed at "H " level, D input appears

Contextual Info: SN74ALVC16601 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS JANUARY 1993 DGG OR DL PACKAGE TOP VIEW UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode

TC4042BP

Abstract: IS902
Contextual Info: TC4042BP/BF C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4042BP/TC4042BF QUAD CLOCKED "D" LATCH TC4042BP/BF contains four circuits of MD" type latches having common CLOCK input and POLARITY input. When POLARITY input is placed at "H" level, D input

Contextual Info: TEXAS INSTR A S I C / M E M O R Y b4E D • 8^1725 ODflEbCH 3 3b M J I SN74ABT7816 64 X 36 X 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS129-JULY1992 Free-Running CLKA and CLKB May Be Asynchronous or Coincident Two Independent 64 x 36 Clocked FIFOs Buffering Data in Opposite Directions

truth table inverter gate 74

Abstract: 74HC74
Contextual Info: 6. HOW TO R E A D MI L T Y PE LOGIC S Y M B O LS A ND TRUTH TA B L ES 6 -1 H o w to read M I L typo L o g ic S y m b o l* Tkble 6-1 shows the MIL type logic symbols used in high-speed CMOS IC This logical chart is based on M1L-STD-806B. Clocked inverters and transmission gates employ specific symbols.

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A - AUGUST 1995 - REVISED APRIL 1998 • Free-Running CLKA and CLKB Can Be Asynchronous or Coincident • Output-Ready and Almost-Empty Flags Synchronized by CLKB • Clocked FIFO Buffering Data From Port A

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

Contextual Info: f¡J PERICOM Product Features: Com mon Features: • PI74FCT16511 and PI74FCT162511 are high-speed, low power devices with high current drive. • Vcc = 5V +10% • Typical tsk o (Output Skew) < 250 ps, clocked mode

IW4042BD

Abstract: IW4042BN
Contextual Info: TECHNICAL DATA IW4042B Quad Clocked «D» Latch High-Voltage Silicon-Gate CMOS IW4042B types contain four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all

Transmission gate IC

Abstract: MIL-STD-806B
Contextual Info: 6. HOW TO R E A D M I L T Y P E LOGIC S Y M B O L S A N D T R U T H T A B L E S 6-1 How to read M IL type Logic Sym bols Tkble 6-1 shows the MIL type logic symbols used in high-speed CMOS IC. This logic chart is based on MIL-STD-806B. Clocked inverters and transmission gate, employ specific symbols.

CY7C4255V

Abstract: CY7C4265V CY7C4275V CY7C4285V CY7C42X5V
Contextual Info: fax id: 5422 CY7C4255V/CY7C4265V CY7C4275V/CY7C4285V PRELIMINARY 8K/16K/32K/64Kx18 Low Voltage Deep Sync FIFOs Features Functional Description The CY7C4255/65/75/85V are high-speed, low-power, first-in first-out FIFO memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to

r2s3

Abstract: CD40192B CD40192BMS CD40193B CD40193BMS
Contextual Info: CD40192BMS CD40193BMS CMOS Presettable Up/Down Counters Dual Clock With Reset December 1992 Features Description • CD40192BMS - BCD Type CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter. The inputs consist of 4 individual jam lines,

Contextual Info: Ordering number : EN8S6089A CMOS LSI No. 5K5089A SAXYO LC374100RP, RM-10/LC374100RP, RM-20LV 4 MEG 524288 words x 8 bits Mask ROM Internal Clocked Silicon Gate Preliminary Overview Package Dimensions The LC374100RP, RM-10 and LC374100RP, RM-20LV are 4 1 94304-bit M ask Program m able Read Only

1 m preset

Contextual Info: SPEED/PACKAGE AVAILABILITY 54 F,W 54LS F,W PIN CONFIGURATION 74 B 74LS B B,F,W PACKAGE INFUT » .E DESCRIPTION 3 v cc r^ D A T * a This monolithic circuit is a synchronous reversible up/down counter having a complexity of 55 equivalent gates. Synchronous operation is provided by having all flip-flops clocked

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227E – FEBRUARY 1993 – REVISED APRIL 1998 D D D D D Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs Read and Write Operations Can Be Synchronized to Independent System

Contextual Info: SN74GTLPH32912 36-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER www.ti.com FEATURES • • • • • • • Member of the Texas Instruments Widebus+ Family UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and

Contextual Info: SN54ABT7819 512 x 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS305D – AUGUST 1994 – REVISED APRIL 1998 D D D D D D D Member of the Texas Instruments Widebus Family Advanced BiCMOS Technology Free-Running CLKA and CLKB Can Be Asynchronous or Coincident

Contextual Info: HD74LS165A Parallel-Load 8-bit Shift Register REJ03D0449–0300 Rev.3.00 Jul.15.2005 The LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual direct data inputs that are enabled by a low level at the shift /

CI 7473

Abstract: A10C SN74ABT7819
Contextual Info: SN74ABT7819 512 x 18 x 2 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS125B —JULY 1992 - REVISED AUGUST 1934 Microprocessor Interface Control Logic Programmable Almost-Full/Almost-Empty Flags Fast Access Times of 9 ns With a 50-pF Load and Simultaneous Switching Data

sf 127d

Abstract: 127D IC51-1324-828 SN74ABT3611 D103E
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident 64 x 36 Clocked FIFO Buffering Data From Port A to Port B Mailbox-Bypass Register In Each Direction

MC889P

Abstract: MC723P MC700P mc723 pj 56 diode MC816P laputa MC816 uln series -driver
Contextual Info: as wfumops \' P L A S T IC M R T L MC700P/800P series M C723P • MC816P J-K flip-flop with a direct clear input in addition to the clocked inputs. CLOCKED INPUT ftPCJIATIM <1> U+KD t-D i l l 3 1 2 - S » 1 (5) 2 - * T [11 <3} 3 -a C Co ^

SN74ACT7811

Abstract: SN74ACT7881 SN74ACT7882 SN74ACT7884
Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227A- FEBRUARY 1993 - REVISED JUNE 1994 Member of the Texas Instruments Wldebus Family * Input-Ready, Output-Ready, and Half-Full Flags Independent Asynchronous Inputs and Outputs Read and Write Operations Can Be